Patents by Inventor Miao-Cheng Liao
Miao-Cheng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9607946Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.Type: GrantFiled: August 15, 2013Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
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Patent number: 9536834Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.Type: GrantFiled: May 30, 2013Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
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Patent number: 9502280Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.Type: GrantFiled: March 6, 2015Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
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Patent number: 9379275Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.Type: GrantFiled: March 30, 2012Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
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Publication number: 20150361547Abstract: A method and an apparatus for forming a cleaning a chemical vapor deposition (CVD) chamber are provided. The method includes providing a chemical vapor deposition (CVD) chamber. The method further includes introducing a remote plasma source into the CVD chamber. The method also includes performing a plasma cleaning process to the CVD chamber by applying a radio-frequency (RF) power in the CVD chamber.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Min-Hui LIN, Kuo-Hsien CHENG, Chia-Hsing CHOU, Miao-Cheng LIAO, Lai-Wan CHONG
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Patent number: 9214514Abstract: Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions.Type: GrantFiled: November 14, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hao Hong, Shiu-Ko Jangjian, Chih-Tsung Lee, Miao-Cheng Liao
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Publication number: 20150179502Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.Type: ApplicationFiled: March 6, 2015Publication date: June 25, 2015Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang Hsiang Ko, Chen-Ming Huang
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Publication number: 20150132913Abstract: Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Min-Hao HONG, Shiu-Ko JANGJIAN, Chih-Tsung LEE, Miao-Cheng LIAO
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Patent number: 9006070Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.Type: GrantFiled: February 25, 2014Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
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Publication number: 20140179071Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.Type: ApplicationFiled: February 25, 2014Publication date: June 26, 2014Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
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Patent number: 8692299Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.Type: GrantFiled: August 24, 2012Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang Hsiang Ko, Chen-Ming Huang
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Publication number: 20140054653Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
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Publication number: 20140007905Abstract: A wafer cleaning system includes a platform, a plurality of wafer holding units over the platform, a front-end rinse nozzle, and a back-end purge unit. The plurality of wafer holding units is set to define a reference plane of wafer holding. The front-end rinse nozzle is above the reference plane and configured to dispense a first rinse fluid toward the reference plane.Type: ApplicationFiled: July 9, 2012Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ren SUN, Hsiang Hsiang KO, Miao-Cheng LIAO, Wei-Yang TSENG
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Publication number: 20130328198Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
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Publication number: 20130260552Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
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Patent number: 8518818Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.Type: GrantFiled: September 16, 2011Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
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Publication number: 20130193540Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.Type: ApplicationFiled: March 30, 2012Publication date: August 1, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
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Patent number: 8455883Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.Type: GrantFiled: May 19, 2011Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Miao-Cheng Liao, Min Hao Hong, Hsiang Hsiang Ko, Kei-Wei Chen, Ying-Lang Wang
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Publication number: 20130069233Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
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Publication number: 20120292639Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Miao-Cheng Liao, Min Hao Hong, Hsiang Hsiang Ko, Kei-Wei Chen, Ying-Lang Wang