Patents by Inventor Miao Jin
Miao Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110900Abstract: A method for rapidly detecting pesticides based on thin-layer chromatography (TLC) and enzyme inhibition principles. The method includes the following steps: cutting a TLC plate into a rectangle, and using one end of the rectangle to contact a sample extract to form a pesticide residue separation area; covering the other end of the rectangle with a small piece cut from filter paper or glass fiber and fixing on a piece of enzyme inhibition reaction test paper to form a pesticide enrichment area; pasting a side of the enzyme inhibition reaction test paper away from the pesticide residue separation area with a piece of filter paper immobilized with a chromogenic agent to form a substrate color development area; and performing color reaction.Type: ApplicationFiled: July 21, 2023Publication date: April 4, 2024Applicant: INSTITUTE OF QUALITY STANDARD AND TESTING TECHNOLOGY FOR AGRO-PRODUCTS, CAASInventors: Miao WANG, Jing WANG, Yunling SHAO, Yongxin SHE, Maojun JIN, Zhen CAO, Shanshan WANG, Lufei ZHENG, Hua SHAO, Fen JIN
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Patent number: 11848369Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.Type: GrantFiled: February 16, 2022Date of Patent: December 19, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
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Publication number: 20220173220Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
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Patent number: 11282936Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.Type: GrantFiled: September 14, 2020Date of Patent: March 22, 2022Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
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Publication number: 20200411656Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
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Patent number: 10777650Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.Type: GrantFiled: April 24, 2017Date of Patent: September 15, 2020Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
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Publication number: 20170309719Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.Type: ApplicationFiled: April 24, 2017Publication date: October 26, 2017Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
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Patent number: 8652951Abstract: Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed.Type: GrantFiled: February 13, 2013Date of Patent: February 18, 2014Assignee: Applied Materials, Inc.Inventors: Yi-Chiau Huang, Jiping Li, Miao Jin, Bingxi Sun Wood, Errol Antonio C. Sanchez, Yihwan Kim
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Publication number: 20130210221Abstract: Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed.Type: ApplicationFiled: February 13, 2013Publication date: August 15, 2013Inventors: YI-CHIAU HUANG, Jiping Li, Miao Jin, Bingxi Sun Wood, Errol Antonio C. Sanchez, Yihwan Kim
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Publication number: 20100203391Abstract: A mesoporous carbon material formed on an electrode surface in an energy storage device, and a method of forming the same are disclosed. The mesoporous carbon material acts as a high surface area ion intercalation medium for the energy storage device, and is made up of CVD-deposited carbon fullerene “onions” and carbon nanotubes (CNTs) that are interconnected in a fullerene/CNT hybrid matrix. The fullerene/CNT hybrid matrix is a high porosity material that is capable of retaining lithium ions in concentrations useful for storing significant quantities of electrical energy. The method, according to one embodiment, includes vaporizing a high molecular weight hydrocarbon precursor and directing the vapor onto a conductive substrate to form a mesoporous carbon material thereon.Type: ApplicationFiled: January 29, 2010Publication date: August 12, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Sergey D. Lopatin, Robert Z. Bachrach, Dmitri A. Brevnov, Christopher Lazik, Miao Jin, Yuri S. Uritsky