Abstract: System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal.

Abstract: The present invention discloses an aryloxy dihalopropenyl ether compound with the structure shown as general formula (I), of which the group definitions can be seen in the specification. The present invention also discloses the use of the compound with general formula (I) as an insecticide in the agricultural field and an insecticidal composition using the compound with general formula (I) as an active component.

Abstract: System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

Abstract: The invention provides a method and a system for determining an end time of uplink back propagation in a mobile communication system to solve a problem of accurately judging the end time of uplink back propagation, wherein the method includes the following steps: sending data with consecutive sequence numbers in a buffer of a packet data convergence protocol (PDCP) module to a serving gateway (S-GW) via an S1 tunnel; sending data with inconsecutive sequence numbers, which is from data with a first inconsecutive sequence number to last data in the buffer of the PDCP module, to a target base station via an uplink back propagation tunnel; generating an end marker datagram; sending the end marker datagram to the target base station via the uplink back propagation tunnel; and receiving, by the target base station, the end marker datagram and determining that the uplink back propagation has ended.

Abstract: Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

Abstract: System and method for regulating a power conversion system. An example system controller for regulating a power conversion system includes a signal generator and a driving component. The signal generator is configured to receive a feedback signal associated with an output signal of a power conversion system and a current sensing signal associated with a primary current flowing through a primary winding of the power conversion system and generate a modulation signal based on at least information associated with the feedback signal and the current sensing signal. The driving component is configured to receive the modulation signal and output a drive signal to a switch based on at least information associated with the modulation signal.

Abstract: Techniques for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver are described herein. In one embodiment, a method for receiving a signal comprises receiving the signal via a receiver input, the received signal comprising a differential signal and a common-mode clock signal. The method also comprises shifting the received signal from a first voltage range to a second voltage range that is lower than the first voltage range, and providing the shifted received signal on a first level-shifted signal line and a second level-shifted signal line. The method further comprises sensing voltage differences between the first and second level-shifted lines to recover the differential signal, and sensing common-mode voltages on the first and second level-shifted signal lines to recover the common-mode clock signal.

Abstract: A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

Abstract: A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

Abstract: System and method for adjusting brightness of one or more cold-cathode fluorescent lamps. The system includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level.

Abstract: The present invention discloses a method and device for reestablishment at packet data convergence protocol (PDCP) layer. On the receiving side of the PDCP layer, the method comprises: clearing resident control messages (501); processing resident service messages, and clearing feedback information generated during processing (502); and resetting a decompressor, and updating configuration of a decryption module (503). On the transmitting side of the PDCP layer, the method comprises: resetting a compressor, and updating configuration of an encryption module; clearing the resident control messages; and reprocessing the resident service messages. With the differentiated processing for the resident messages at the PDCP layer during the reestablishment, the present invention can avoid the abnormal mode switching of the compressor, and accelerate the user plane restoration after the reestablishment.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor.

Abstract: System and method for driving one or more cold-cathode fluorescent lamps. For example, the method includes generating at least one drive signal associated with a signal frequency, the signal frequency being equal to a first predetermined frequency, receiving a current-sensing signal, the current-sensing signal being associated with a lamp current for the one or more cold-cathode fluorescent lamps in response to at least the first predetermined frequency, and determining whether the current-sensing signal is larger than a first threshold in magnitude, the current-sensing signal being related to the first predetermined frequency.

Abstract: The present invention discloses an aryloxy dihalopropenyl ether compound with the structure shown as general formula (I), of which the group definitions can be seen in the specification. The present invention also discloses the use of the compound with general formula (I) as an insecticide in the agricultural field and an insecticidal composition using the compound with general formula (I) as an active component.

Abstract: In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.