Patents by Inventor Miao Rao

Miao Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for flexible and repeatable pre-route generation
    Patent number: 8627255
    Abstract: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: January 7, 2014
    Assignee: Oracle International Corporation
    Inventors: Kiran Vedantam, James G. Ballard, Miao Rao, Guneet Singh, Wanyun Singh
  • METHODS AND SYSTEMS FOR FLEXIBLE AND REPEATABLE PRE-ROUTE GENERATION
    Publication number: 20120110537
    Abstract: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: Oracle International Corporation
    Inventors: Kiran Vedantam, James Ballard, Miao Rao, Guneet Singh, Wanyun Shih
  • Low power memory design with asymmetric bit line driver
    Patent number: 6707721
    Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: March 16, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant
  • Low power memory design with asymmetric bit line driver
    Publication number: 20030174535
    Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 18, 2003
    Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant