Abstract: A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up.

Abstract: Embodiments of the present disclosure provide optical link handshake techniques and configurations. In one embodiment, an optical module includes a laser driver corresponding with a channel of the optical module, a signal detector corresponding with the channel, and a link handshake state machine configured to control the laser driver to generate a connect pulse of a link handshake process to test an optical link between the channel and a corresponding channel of another optical module and monitor the signal detector to detect a connect pulse from the another optical module. Other embodiments may be described and/or claimed.

Abstract: A system includes two optical modules that perform auto-setting of the optical links between the optical modules. One optical module sends an optical signal with a test pattern to the other optical module. If the receiving module determines that the test pattern is successfully received, it sends a pass indication to the transmitting module, and the transmitting module can configure its driver path in accordance with a transmit current setting used to transmit the test pattern. If the test pattern is not successfully received, the receiving module sends a fail indication, and the transmitting module can increase the transmit current setting and resend the test pattern. When the system includes multiple optical channels, one channel can be tested while feedback is provided on another channel. The system can iterate through all optical channels until they are all configured.

Abstract: Described is a method and apparatus for generating a mid-level reference signal and for cancelling amplifier offset in an optical communication system without DC-balancing of optical data. The apparatus comprises an optical-to-electrical converter to receive an optical signal and to generate an electrical signal; an amplifier to receive the electrical signal and to generate an output signal based on a reference signal; a feedback mechanism to be enabled during a training phase only and to generate a control signal from the output signal; and a counter logic having a digital-to-analog converter to generate the reference signal based on the control signal.

Abstract: A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up.

Abstract: A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up.

Abstract: Described is a method and apparatus for generating a mid-level reference signal and for cancelling amplifier offset in an optical communication system without DC-balancing of optical data. The apparatus comprises an optical-to-electrical converter to receive an optical signal and to generate an electrical signal; an amplifier to receive the electrical signal and to generate an output signal based on a reference signal; a feedback mechanism to be enabled during a training phase only and to generate a control signal from the output signal; and a counter logic having a digital-to-analog converter to generate the reference signal based on the control signal.

Abstract: Embodiments introduce redundant optical channels to significantly extend the lifetime of parallel optical transceivers. A plurality of transmitters, N, transmit on a plurality of optical channels, where N is an integer number of optical channels greater than 1. One or more redundant channels, M, are also provided. N+M multiple input shift registers provide multiple paths for signals from each of the transmitters to connect to N+M laser diodes. In the event up to M of the N+M laser diodes fail, the multiple input shift registers connect the N transmitters to functioning ones of the N+M laser diodes thus extending the life of the device. A corresponding scheme is also described for the receiver side.

Abstract: A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up.

Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.

Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.

Abstract: Briefly, in accordance with one or more embodiments, a transimpedance amplifier of an optical transceiver or the like has a feedback element in a feedback arrangement and is capable of receiving an electrical current from an optical-to-electrical converter to generate an output voltage in response to the electrical current. A control circuit coupled to the feedback element is capable of providing a control signal to control a bias current of the transimpedance amplifier to maintain DC current flowing through the feedback element at or near zero by changing the bias current in response to the control circuit detecting a non-zero DC current flowing through the feedback element.

Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.

Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.

Abstract: In one embodiment, the present invention includes an apparatus having a current mirror with a current source coupled to a first terminal and an output current to flow from an output terminal, a laser coupled to the output terminal to be biased by the output current, and a comparator to compare a voltage of the first terminal to the voltage of the output terminal and gate the current mirror based on the comparison. Other embodiments are described and claimed.

Abstract: Embodiments introduce redundant optical channels to significantly extend the lifetime of parallel optical transceivers. A plurality of transmitters, N, transmit on a plurality of optical channels, where N is an integer number of optical channels greater than 1. One or more redundant channels, M, are also provided. N+M multiple input shift registers provide multiple paths for signals from each of the transmitters to connect to N+M laser diodes. In the event up to M of the N+M laser diodes fail, the multiple input shift registers connect the N transmitters to functioning ones of the N+M laser diodes thus extending the life of the device. A corresponding scheme is also described for the receiver side.

Abstract: A laser driver for generating drive waveforms that are suitable for driving a single VCSEL or an array of VCSELs. A digital controller is integrated into the laser driver and is utilized to initially program and selectively adjust during the operation of the driver one or more of the following VCSEL drive waveform parameters: (1) bias current, (2) modulation current, (3) negative peaking depth, and (4) negative peaking duration. The laser driver has an aging compensation mechanism for monitoring the age of the laser and for selectively adjusting the dc and ac parameters of the VCSEL drive waveform to compensate for the aging of the laser. The laser driver also has a temperature compensation mechanism for monitoring the temperature of the driver IC and selectively adjusting the dc and ac parameters of the VCSEL drive waveform to compensate for the changes in temperature.

Abstract: Systems and methods of converting data streams from one clocking domain to another are described. In one aspect, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle at an average rate RIN, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at an average rate ROUT, wherein M has an integer value of at least 1 and M≠N.

Abstract: A laser driver for generating drive waveforms that are suitable for driving a single VCSEL or an array of VCSELs. A digital controller is integrated into the laser driver and is utilized to initially program and selectively adjust during the operation of the driver one or more of the following VCSEL drive waveform parameters: (1) bias current, (2) modulation current, (3) negative peaking depth, and (4) negative peaking duration. The laser driver has an aging compensation mechanism for monitoring the age of the laser and for selectively adjusting the dc and ac parameters of the VCSEL drive waveform to compensate for the aging of the laser. The laser driver also has a temperature compensation mechanism for monitoring the temperature of the driver IC and selectively adjusting the dc and ac parameters of the VCSEL drive waveform to compensate for the changes in temperature.