Patents by Inventor Miau-Shing Tsay

Miau-Shing Tsay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Release accumulative charges by tuning ESC voltages in via-etchers
    Patent number: 8263495
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 11, 2012
    Assignee: Global Unichip Corp.
    Inventors: Ting-Yi Lin, Chi-Yuan Wen, Chuang Tse Chuan, Miau-Shing Tsay, Ming Li Wu
  • Release Accumulative Charges by Tuning ESC Voltages in Via-Etchers
    Publication number: 20110151669
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Ting-Yi Lin, Chi-Yuan Wen, Chuang Tse Chuan, Miau-Shing Tsay, Ming Li Wu