Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: The present invention relates to new attenuated M. bovis bacteria strains. Moreover, the present invention also provides immunogenic compositions comprising live bacteria of an of those attenuated M. bovis bacteria strain, their manufacture and use for the treatment and prophylaxis of M. bovis infections.

Abstract: In order to render possible a compact means for power distribution and fuse protection on the basis of a printed circuit board, the apparatus has a multiple fuse arrangement which comprises a plurality of fuses and is connected to a plurality of output contacts. Furthermore, a printed circuit board is provided, which has a feed plate, which is connected to the multiple fuse arrangement, in particular by means of plug-in contact elements, arranged on one of its sides. The output contacts are arranged on that side of the printed circuit board which is opposite the feed plate.

Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

Abstract: The present invention is directed towards a method for the production of 2,4,6-trimercapto-1,3,5-triazine (TMT-H3). In particular, the method of the subject matter relates to the operation of acidifying the salts of 2,4,6-trimercapto-1,3,5-triazine in aqueous solution and in a defined pH range.

Abstract: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.

Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract: The present application relates to novel heterocyclic compounds, to processes for their preparation, and to their use as crop protection agents, particularly for controlling animal pests.

Abstract: Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.

Abstract: In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is selectively removed from above the upper surface of the conductive region to expose the upper surface of the conductive region. After the selectively removing process, at least a portion of the liner remains over the lower surface of the trench and the sidewalls of the trench and the via hole. A wet etch can then be performed to etch a recess in the conductive region. A conductive material is then formed within the damascene structure. This conductive material physically contacts the conductive region and is separated from the dielectric layer by the remaining portion of the liner.

Abstract: An apparatus to capture snakes or small animals has an inner extensible coil spring support structure having shape memory. The support structure is overlaid or enclosed by a flexible mesh netting having open spaces whereby the snakes may pass through the spaces only when moving in a first forward direction. A deployment container houses the support structure and the netting when the support structure is in a retracted position. Multiple layers of concentrically arranged netting with different mesh sizes may be used to enclose the support structure.

Abstract: In order to render possible a compact means for power distribution and fuse protection on the basis of a printed circuit board, the apparatus has a multiple fuse arrangement (10) which comprises a plurality of fuses (14) and is connected to a plurality of output contacts (18). Furthermore, a printed circuit board (2) is provided, which has a feed plate (4), which is connected to the multiple fuse arrangement (10), in particular by means of plug-in contact elements (8), arranged on one of its sides. The output contacts (18) are arranged on that side of the printed circuit board (2) which is opposite the feed plate (4).

Abstract: Access nodes (1) for giving client devices (2,3) access to internet networks (5) comprise detectors (11) for detecting request messages in client information defining requests for receiving media contents and are provided with processors (12) for processing detections of the request messages for gathering statistical information about the media contents. The statistical information comprises viewing figures per media content. Further request messages in the client information define further requests for finishing receptions of the media contents for gathering further statistical information. The further statistical information comprises timing figures per media content. Data messages define client data with respect to the media contents for gathering yet further statistical information. The yet further statistical information comprises appreciation figures and/or yet further viewing figures per media content.

Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

Abstract: A method to preserve the ordering of data packets of a same flow (P1-P4, P7, P8) passing either through a control plane (CP) or through a data plane (DP) of a telecommunication network element. The method comprises the step of, when the control plane starts processing the new flow, the control plane controls the data plane to latch any other packet belonging to this flow by sending a first control packet (C1) to said data plane. When the processing is completed, the control plane controls the data plane to release the latched packets by sending a second control packet (C3) to said data plane. The present method is particularly applicable to Ethernet frames, where it is also not allowed to reorder frames belonging to a same ‘Ethernet flow’.

Abstract: The present invention relates to a transformer with a coil body accommodating at least one primary coil and one secondary coil. It is the object of the present invention to provide a transformer which, using the smallest possible amount of high-grade insulation material, ensures good insulation while remaining compact and easily assembled. The object is achieved by a transformer of the above type which is characterized in that the coil body comprises at least one primary part, accommodating the primary coil, and one secondary part, accommodating the secondary coil, and wherein at least one section of the primary part can be covered by at least one section of the secondary part. This section of the secondary part performs the function of the fire-protection housing for the primary part of the transformer.

Abstract: A hub drive includes an in-hub motor and a shifting in-hub transmission coupled with the motor. A hub drive wheel assembly includes a wheel comprising a hub, an in-hub motor, and a shifting in-hub transmission having an input attached to the motor and an output attached to the wheel. A vehicle includes a chassis, a wheel comprising a hub, an in-hub motor, and a shifting in-hub transmission having an input attached to the motor and an output attached to the wheel for rotating the wheel with respect to the chassis. A method includes providing a shifting transmission and a motor coupled with the transmission in a hub of a wheel, providing electrical power to the motor, and rotating the motor with the electrical power. The method further includes rotating the transmission with the motor and rotating the wheel with the transmission.

Abstract: A vehicle includes a chassis and a plurality of wheel assemblies articulated with the chassis, each of the plurality of wheel assemblies comprising a rotatable wheel spaced away from the chassis. A vehicle includes a chassis and an articulated suspension system mounted to the chassis. A method includes comprising articulating at least one of a plurality of wheel assemblies with a chassis, each of the wheel assemblies including a rotatable wheel spaced apart from the chassis. A vehicle includes a chassis and articulatable means for rolling the chassis along a path.

Abstract: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.

Abstract: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.