Patents by Inventor Michaël Nicolaidis
Michaël Nicolaidis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8230279Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: GrantFiled: February 19, 2011Date of Patent: July 24, 2012Assignee: iRoctechnologiesInventor: Michael Nicolaidis
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Patent number: 8042011Abstract: One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.Type: GrantFiled: April 28, 2009Date of Patent: October 18, 2011Assignee: Synopsys, Inc.Inventors: Michael Nicolaidis, Silmane Boutobza
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Publication number: 20110167324Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: ApplicationFiled: February 19, 2011Publication date: July 7, 2011Applicant: iROC Technologies CorporationInventor: Michael Nicolaidis
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Patent number: 7904772Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: GrantFiled: June 17, 2009Date of Patent: March 8, 2011Assignee: iRoc TechnologiesInventor: Michael Nicolaidis
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Publication number: 20100275074Abstract: One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Applicant: SYNOPSYS, INC.Inventors: Michael Nicolaidis, Slimane Boutobza
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Patent number: 7778001Abstract: An integrated circuit chip comprising a number of semiconductor components exhibiting parasitic components through which a short-circuit between the circuit supply voltage and ground could occur, wherein said semiconductor components are distributed in elementary blocks, each elementary block being independently connected, for its power supply, to the supply or ground lines of the main supply network of the integrated circuit by a current-limiting device capable of stopping a short-circuit starting in the considered block, and each block being sized so that logic errors occurring in this block are correctable by error-correction means.Type: GrantFiled: June 16, 2006Date of Patent: August 17, 2010Assignee: IROC TechnologiesInventor: Michaël Nicolaidis
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Publication number: 20090259897Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: ApplicationFiled: June 17, 2009Publication date: October 15, 2009Applicant: iROC TechnologiesInventor: Michael Nicolaidis
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Patent number: 7565590Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: GrantFiled: June 19, 2007Date of Patent: July 21, 2009Assignee: iROC TechnologiesInventor: Michael Nicolaidis
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Publication number: 20090128975Abstract: An integrated circuit chip comprising a number of semiconductor components exhibiting parasitic components through which a short-circuit between the circuit supply voltage and ground could occur, wherein said semiconductor components are distributed in elementary blocks, each elementary block being independently connected, for its power supply, to the supply or ground lines of the main supply network of the integrated circuit by a current-limiting device capable of stopping a short-circuit starting in the considered block, and each block being sized so that logic errors occurring in this block are correctable by error-correction means.Type: ApplicationFiled: June 16, 2006Publication date: May 21, 2009Inventor: Michael Nicolaidis
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Patent number: 7380192Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: GrantFiled: March 8, 2000Date of Patent: May 27, 2008Assignee: iROC TechnologiesInventor: Michaël Nicolaidis
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Publication number: 20080028278Abstract: The invention concerns a digital circuit architecture including combinatorial circuits, and memory circuits. Systems for protection against different perturbations are used for different types of circuits based upon the functionality of the circuits.Type: ApplicationFiled: September 27, 2007Publication date: January 31, 2008Applicant: iROC TechnologiesInventor: Michael Nicolaidis
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Publication number: 20070250748Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.Type: ApplicationFiled: June 19, 2007Publication date: October 25, 2007Applicant: iROC TechnologiesInventor: Michael Nicolaidis
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Patent number: 7126320Abstract: A circuit for evaluating characteristics of duration and/or shape of an electric pulse induced in an element of an integrated circuit comprising an assembly of elements, each element being likely to receive an occasional external disturbance generating an electric pulse in the element, and a measurement circuit connected to the elements to determine said characteristics of an electric pulse generated in one of the elements.Type: GrantFiled: August 26, 2003Date of Patent: October 24, 2006Assignee: iROC TechnologiesInventor: Michael Nicolaidis
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Patent number: 7124348Abstract: The invention concerns a data storage method enabling error detection and correction in an organized storage for reading and writing words of a first number (m) of bits and optionally for modifying only part of such a word, comprising the following steps which consist in: associating an error detection and correction code with a group of a second number (k?1) of words; and at each partial writing in the group of words, calculating a new code of the modified group of words; performing a verification operation and, if an error occurs, carrying out an error correction of the modified word and/or of the new code.Type: GrantFiled: October 31, 2002Date of Patent: October 17, 2006Assignee: iROC TechnologiesInventor: Michael Nicolaidis
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Patent number: 7093176Abstract: A programmable built in self test, BIST, system for testing a memory, comprises an instruction register formed in the same chip as the memory; a circuit for loading the register by successive instructions, each instruction comprising at least one address control field, a first number (m) of operation fields, a number-of-operations field specifying a second number t+1, with t+1?m; a circuit controlled by the address control field to determine successive addresses; and a cycle controller for executing, for each successive address, the second number (t+1) of successive operations, each of which is determined by one of the t+1 first operation fields.Type: GrantFiled: March 3, 2003Date of Patent: August 15, 2006Assignee: iRoC TechnologiesInventors: Michaël Nicolaidis, Slimane Boutobza
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Patent number: 7073102Abstract: A device for reconfiguring faults in a circuit comprised of several units and comprising storage means for storing the fault locations, connection/disconnection means for disconnecting faulty units and connecting in their place fault-free units, and means for generating control signals of the connection/disconnection means, responding to the content of the storage means. According to this method, each unit is divided into several portions; in a test phase, fault tests are carried out for the different units, and the test results of the different portions of the units are stored in the storage means; and in a use phase aiming at the use of given unit portions, said control signals are determined by the content of the storage means corresponding to these unit portions.Type: GrantFiled: November 1, 2002Date of Patent: July 4, 2006Assignee: LROC TechnologiesInventor: Michaël Nicolaidis
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Patent number: 6946985Abstract: The invention CONCERNS a device for reconfiguring an assembly of N basic electronic modules associated with k redundant modules comprising: N multiplexers each having a first terminal (di) capable of being connected to k+1 second terminals connected to the k+1 input/output terminals of a sequenced group of modules consisting of a basic module (Ui) and k other modules; N+k triggers (Fi) indicating a good or faulty condition of one of the N+k modules; and logic means associated with each multiplexer of rank j, where j is an integer ranging between 0 and N, to determine the number of triggers of rank 0 to j indicating a faulty condition, to determine the number of modules of the sequenced group associated with the module of rank j, to be counted to find a number of good modules equal to the first number, and to convert the first terminal of the multiplexer to its second terminal of rank equal to the second number.Type: GrantFiled: February 12, 2002Date of Patent: September 20, 2005Assignee: IROC TechnologiesInventor: Michael Nicolaidis
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Publication number: 20050028061Abstract: The invention concerns a data storage method enabling error detection and correction in an organized storage for reading and writing words of a first number (m) of bits and optionally for modifying only part of such a word, comprising the following steps which consist in: associating an error detection and correction code with a group of a second number (k?1) of words; and at each partial writing in the group of words, calculating a new code of the modified group of words; performing a verification operation and, if an error occurs, carrying out an error correction of the modified word and/or of the new code.Type: ApplicationFiled: October 31, 2002Publication date: February 3, 2005Inventor: Michael Nicolaidis
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Publication number: 20040255204Abstract: The invention concerns a digital circuit architecture comprising combinational circuits (10, 12), short-term memory circuits (11) not capable of storing data for more than k operating cycles, long-term memory circuits (13) capable of storing data for more than k operating cycles of the circuit. Systems for protection against different perturbations are used for the different types of circuits and based on the functionality of said circuits.Type: ApplicationFiled: April 8, 2004Publication date: December 16, 2004Inventor: Michael Nicolaidis
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Publication number: 20040080343Abstract: A circuit for evaluating characteristics of duration and/or shape of an electric pulse induced in an element of an integrated circuit comprising an assembly of elements, each element being likely to receive an occasional external disturbance generating an electric pulse in the element, and a measurement circuit connected to the elements to determine said characteristics of an electric pulse generated in one of the elements.Type: ApplicationFiled: August 26, 2003Publication date: April 29, 2004Applicant: iROC TechnologiesInventor: Michael Nicolaidis