Abstract: A tester interface unit comprising a test hardware module. The test hardware module may have a simple construction, relying on control and/or signal processing in one or more tester instruments to generate or analyze test signals for a device under test. The test hardware module may be disposed within the tester interface unit, providing a short and high integrity signal path length to the device under test. The tester interface unit may include a purge gas chamber and a cooling chamber, with the hardware module penetrate a separator between those chambers, sealing an opening between the purge gas chamber and the cooling chamber. A heat spreader may move heat generated on the portion of the test hardware module in the purge gas chamber to the cooling chamber.

Abstract: A tester interface unit comprising a test hardware module. The test hardware module may have a simple construction, relying on control and/or signal processing in one or more tester instruments to generate or analyze test signals for a device under test. The test hardware module may be disposed within the tester interface unit, providing a short and high integrity signal path length to the device under test. The tester interface unit may include a purge gas chamber and a cooling chamber, with the hardware module penetrate a separator between those chambers, sealing an opening between the purge gas chamber and the cooling chamber. A heat spreader may move heat generated on the portion of the test hardware module in the purge gas chamber to the cooling chamber.

Abstract: An example test system includes: a manifold including fluid channels, where the fluid channels are for holding coolant; a quick disconnect mechanically coupled to the manifold, where the quick disconnect includes a channel for passing coolant between a fluid channel and a test board; a containment plate mechanically coupled to the manifold, and a cover over at least part of the quick disconnect, where the cover is hermetically sealed to the quick disconnect and to the containment plate to thereby form a containment chamber.

Abstract: An example test system includes: a pin electronics board for exchanging signals with a device under test (DUT), where the pin electronics board includes first electrical contacts; an interposer between the pin electronics board and a paddle board, where the paddle board includes second electrical contacts, and where the interposer includes electrical connectors for use in establishing electrical pathways between the first electrical contacts and the second electrical contacts; and an actuator configured to force the paddle board and the interposer to make contact so as to cause the electrical connectors to contact the second electrical contacts and thereby establish the electrical pathways.

Abstract: An example test system includes: a manifold including fluid channels, where the fluid channels are for holding coolant; a quick disconnect mechanically coupled to the manifold, where the quick disconnect includes a channel for passing coolant between a fluid channel and a test board; a containment plate mechanically coupled to the manifold, and a cover over at least part of the quick disconnect, where the cover is hermetically sealed to the quick disconnect and to the containment plate to thereby form a containment chamber.

Abstract: An example test system includes: a pin electronics board for exchanging signals with a device under test (DUT), where the pin electronics board includes first electrical contacts; an interposer between the pin electronics board and a paddle board, where the paddle board includes second electrical contacts, and where the interposer includes electrical connectors for use in establishing electrical pathways between the first electrical contacts and the second electrical contacts; and an actuator configured to force the paddle board and the interposer to make contact so as to cause the electrical connectors to contact the second electrical contacts and thereby establish the electrical pathways.

Abstract: This invention provides a manipulator for positioning a test head relative to a prober or other reference. The manipulator has a frame; a linkage coupled to the frame and including first and second links having freedom of rotation about respective pivots and a third link coupled to the first and second links such that the third link has translational and rotational degrees of freedom of movement; and an adaptor coupled to the third link and configured to attach to a test head. The invention also provides a method of controlling the manipulator.

Abstract: This invention provides a manipulator for positioning a test head relative to a prober or other reference. The manipulator has a frame; a linkage coupled to the frame and including first and second links having freedom of rotation about respective pivots and a third link coupled to the first and second links such that the third link has translational and rotational degrees of freedom of movement; and an adaptor coupled to the third link and configured to attach to a test head. The invention also provides a method of controlling the manipulator.

Abstract: This invention provides a manipulator for positioning a test head relative to a prober or other reference. The manipulator has a frame; a linkage coupled to the frame and including first and second links having freedom of rotation about respective pivots and a third link coupled to the first and second links such that the third link has translational and rotational degrees of freedom of movement; and an adaptor coupled to the third link and configured to attach to a test head. The invention also provides a method of controlling the manipulator.

Abstract: A probe assembly for use with a calibration/validation robot to calibrate/validate a plurality of semiconductor tester channels is disclosed. The probe assembly includes a bracket adapted for mounting to the robot and a probe element for engaging test points disposed on the semiconductor tester channels. A magnetic attach/release mechanism cooperates with the bracket and probe element to allow for the separation of the probe element from the bracket whenever the probe element meets a force that exceeds a predetermined value.

Abstract: A compliance assembly is disclosed for use in a semiconductor tester testhead stand. The compliance assembly includes an airspring having compliance along a plurality of axes and a containment vessel adapted for receiving the airspring. The containment vessel includes walls that, when the airspring is loaded, control the compliance along the plurality of axes.

Abstract: A probe assembly for use with a calibration/validation robot to calibrate/validate a plurality of semiconductor tester channels is disclosed. The probe assembly includes a bracket adapted for mounting to the robot and a probe element for engaging test points disposed on the semiconductor tester channels. A magnetic attach/release mechanism cooperates with the bracket and probe element to allow for the separation of the probe element from the bracket whenever the probe element meets a force that exceeds a predetermined value.

Abstract: A compliance assembly is disclosed for use in a semiconductor tester testhead stand. The compliance assembly includes an airspring having compliance along a plurality of axes and a containment vessel adapted for receiving the airspring. The containment vessel includes walls that, when the airspring is loaded, control the compliance along the plurality of axes.

Abstract: A powder bed (32) is built up by repeated deposition of a slurry that contains powder. Layers are made by depositing a liquid dispersion of the desired powdered material, which then slip-casts into the forming powder bed to make a new layer (34). The slurry may be deposited in any suitable manner, such as by raster or vector scanning, or by a plurality of simultaneous jets that coalesce before the liquid slip-casts into the bed, or by individual drops, the deposits of which are individually controlled, thereby generating a regular surface for each layer.

Abstract: A semiconductor tester is disclosed that is adapted for testing semiconductor devices disposed on a handling apparatus. The semiconductor tester includes a tester housing defining a self-supporting frame and formed with an externally accessible opening adapted for receiving the handling apparatus. A test controller is disposed within the housing and carried by the frame. Pin electronics including tester circuitry are responsive to the test controller and proximately coupled thereto and mounted to the frame. A docking apparatus is disposed above the opening and is adapted to couple the tester circuitry to the handling apparatus.