Abstract: An optical input system for correcting astigmatism introduced by off-axis reflectors in a spectrograph includes an aspheric mirror producing a correcting factor which compensates for the spectrograph distortions and enables the spectrograph to produce multiple astigmatic light images at its two-dimensional charge-coupled-device output.

Abstract: A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled.

Abstract: The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments to physically divide the memory cell array into sub-arrays, and multiplexing the bit line segments of groups of neighboring bit lines are multiplexed to respective data lines. "Early" address bits control row decoders which select a row of memory cells in each sub-array to assert data signals on the bit line segments in each sub-array. "Late" address bits control the multiplexing of the data signals on the bit line segments to the data lines. By segmenting the bit lines, the number of "late" address bits is increased relative to the number of "early" address bits to increase the memory access speed in data processing systems that employ virtual addressing but store data in cache memory in association with physical addresses.

Abstract: A heat exchange apparatus (10) formed of a plurality of heat exchange modules (20) mounted together in side-by-side relationship to form a box-like array. Each heat exchange module (20) houses a multiplicity of heat exchange tubes (44) which provide a flow passage through which a first heat exchange fluid, such as air, is passed in heat exchange relationship with a second heat exchange fluid, such as flue gas, passing through the heat exchange apparatus over the heat exchange tubes.

Abstract: A recuperative tubular heat exchanger comprised of a plurality of tube-bundle heat exchange modules (20) stacked in a spaced array and interconnected by U-shaped, open-end header conduits (30) to form a serpentine flowpath through which a fluid to be heated is passed in heat exchange relationship with a heating fluid passing in cross flow over the tube bundle modules. The interconnected modules together with the header conduits form an integral assembly which is free to slide on support beams (26) so as to float within the housing (12) of the heat exchanger in response to the thermal deformation of the tube bundle modules.