Patents by Inventor Michael A. Church
Michael A. Church has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133236Abstract: A lighted architectural-structure covering is disclosed. In one example of an embodiment, an architectural-structure covering includes a light source arranged and configured to illuminate at least a portion of the architectural-structure covering. The architectural-structure covering may include first and second coverings. The light source is arranged and configured to direct light onto the second covering, which is arranged and configured to reflect, redistribute, etc. the received light toward the interior space of the room in which the architectural-structure covering is located. Thus arranged, the architectural-structure covering may be used to create, for example, diffused-lighting effects.Type: ApplicationFiled: March 22, 2021Publication date: April 25, 2024Applicant: Hunter Douglas Inc.Inventors: Coty CHURCH, Michael J. SIEBENALLER, Kevin M. DANN, Christopher M. WHITE
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Publication number: 20240093857Abstract: A lighted architectural-structure covering is disclosed. In one example of an embodiment, an architectural-structure covering includes a light source arranged and configured to illuminate at least a portion of the architectural-structure covering. The architectural-structure covering may include first and second coverings. The light source is arranged and configured to direct light onto the second covering, which is arranged and configured to reflect, redistribute, etc. the received light toward the interior space of the room in which the architectural-structure covering is located. Thus arranged, the architectural-structure covering may be used to create, for example, diffused-lighting effects.Type: ApplicationFiled: October 8, 2020Publication date: March 21, 2024Applicant: Hunter Douglas Inc.Inventors: Michael J. Siebenaller, Coty Church, Kevin M. Dann, Christopher M. White
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Publication number: 20230256818Abstract: A drive spline defines an inner profile configured to receive and mate with a drive axle and an outer profile configured to mate with a wheel hub. A cage surrounds and is engaged with the outer profile of the drive spline. The cage retains the drive spline axially and radially in position relative to the outer profile. A cap is coupled to an end of the wheel hub connecting device opposite the drive spline. The cap encloses the end of the hub connecting device.Type: ApplicationFiled: February 10, 2023Publication date: August 17, 2023Inventors: John Medeiros, Michael Church, Adam Reiner, Russell Conine
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Publication number: 20200356399Abstract: A virtual control unit according to the AUTOSAR standard, including a service layer, an ECU abstraction layer, and a microcontroller abstraction layer. It is provided according to invention that the virtual control unit additionally comprises a hardware layer that is configured to simulate at least one hardware component. A virtual control unit is provided in this way which enables easy use of environment models for HIL tests and software testing and a fast simulation.Type: ApplicationFiled: May 8, 2020Publication date: November 12, 2020Applicant: dSPACE digital signal processing and control engineering GmbHInventors: Ulrich KIFFMEIER, Markus SUEVERN, Stuart Michael CHURCH
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Publication number: 20140175773Abstract: A flow rectifier assembly including a manifold with a variable orifice disposed therein. Further, the flow rectifier assembly includes one or more valves disposed in the manifold and fluidly connected to the variable orifice to provide a uni-directional flow over the variable orifice. Each of the one or more valves includes a poppet. A fly-cut recess defined in the manifold includes a seat for resting the poppet.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Caterpillar Inc.Inventors: David E. Ault, Moses I. Akpan, Michael A. Church, Landin T. Fisher
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Publication number: 20110176368Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.Type: ApplicationFiled: March 31, 2011Publication date: July 21, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Alexander Kalnitsky, Michael Church
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Publication number: 20090207655Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.Type: ApplicationFiled: April 24, 2009Publication date: August 20, 2009Applicant: INTERSIL AMERICAS INC.Inventors: Alexander Kalnitsky, Michael Church
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Patent number: 7542342Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.Type: GrantFiled: August 23, 2006Date of Patent: June 2, 2009Assignee: Intersil Americas Inc.Inventors: Alexander Kalnitsky, Michael Church
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Publication number: 20090035910Abstract: This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed.Type: ApplicationFiled: October 11, 2007Publication date: February 5, 2009Applicant: INTERSIL AMERICAS, INC.Inventor: Michael Church
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Publication number: 20090032885Abstract: The present disclosed integrated circuit includes a substrate having a top surface, a buried N type layer in the substrate, N type contact region extending from the surface to the buried N type region, a buried P type region abutting and above the buried N type region in the substrate, a P type contact region extending from the surface to the buried P type region, and an N type device region in the surface and above the buried P type region. The P type impurity of the buried P type region including an impurity of a lower coefficient of diffusion than the coefficient of diffusion of the impurities of the P type contact region.Type: ApplicationFiled: October 23, 2007Publication date: February 5, 2009Applicant: INTERSIL AMERICAS, INC.Inventor: Michael Church
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Publication number: 20080246305Abstract: An armrest for an automotive type door is provided. The armrest includes a frame member engageable with such automotive type door at a predetermined location thereon. Such frame member is manufactured from a first predetermined material and has a first predetermined size and a first predetermined shape. A padding member is manufactured from a second predetermined material and has a second predetermined size and a second predetermined shape. Such padding member is operably connected to such frame member at a predetermined location thereon.Type: ApplicationFiled: March 27, 2008Publication date: October 9, 2008Inventor: Michael Church
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Publication number: 20070247915Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.Type: ApplicationFiled: August 2, 2006Publication date: October 25, 2007Applicant: Intersil Americas Inc.Inventors: Alexander Kalnitsky, Michael Church
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Publication number: 20070187837Abstract: A semiconductor structure is provided. In one embodiment, the structure comprises at least one active device located in a substrate and directly under a bond pad. A conductor is located between the bond pad and the substrate. The conductor has a plurality of gaps filled with insulating material. The insulating material is harder than the conductor.Type: ApplicationFiled: April 19, 2007Publication date: August 16, 2007Applicant: INTERSIL AMERICAS INC.Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman, David Decrosta, Robert Lomenick, Chris McCarty
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Publication number: 20070184645Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: ApplicationFiled: April 19, 2007Publication date: August 9, 2007Applicant: INTERSIL AMERICAS INC.Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman Jr., David Decrosta, Robert Lomenick, Chris McCarty
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Publication number: 20070121381Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.Type: ApplicationFiled: August 23, 2006Publication date: May 31, 2007Applicant: Intersil Americas Inc.Inventors: Alexander Kalnitsky, Michael Church
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Publication number: 20060099823Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.Type: ApplicationFiled: December 19, 2005Publication date: May 11, 2006Applicant: Intersil Americas Inc.Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman, David Decrosta, Robert Lomenick, Chris McCarty
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Publication number: 20060097293Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.Type: ApplicationFiled: November 7, 2005Publication date: May 11, 2006Inventors: Stephen Gaul, Michael Church, James Vinson
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Publication number: 20050042853Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.Type: ApplicationFiled: October 31, 2003Publication date: February 24, 2005Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman, David Decrosta, Robert Lomenick, Chris McCarty