Patents by Inventor Michael A. Comai

Michael A. Comai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shrink test mode to identify Nth order speed paths
    Patent number: 7607061
    Abstract: In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 20, 2009
    Assignee: Global Founderies Inc.
    Inventors: Michael A. Comai, Philip E. Madrid
  • Shrink Test Mode to Identify Nth Order Speed Paths
    Publication number: 20090037788
    Abstract: In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 5, 2009
    Inventors: Michael A. Comai, Philip E. Madrid