Abstract: Source data can be preconditioned to perform a packed min/max operation. A first selector can be coupled to a first invertor and a first input. A second selector can be coupled to a second invertor and a second input. An adder can be coupled to said first selector and said second selector. A third selector can be coupled to said adder, the first input, and the second input.

Abstract: A computer system is described. The computer system includes a bus, a CPU coupled to the bus, and a memory coupled to the bus. A peripheral device is coupled to the bus for performing a predefined peripheral operation. A logic is coupled to the bus and the peripheral device for causing the CPU to be interrupted to control the peripheral device for the peripheral operation when the logic receives a request for the peripheral operation. The logic does not control the peripheral device to perform the peripheral operation. The peripheral operation of the peripheral device is only controlled by the CPU. The request may be generated by a software program running on the CPU. The request may also be generated by the peripheral device. Although the CPU is controlling the peripheral operation, the existing peripheral controller-based application software can still be used. A method for controlling the peripheral device for the peripheral operation is also described.

Abstract: An interface card has an interface logic block for interfacing a peripheral device with a computer host and for selecting either a common memory mode or an audio mode where the computer host can enable or disable a common memory read or write operation in the common memory mode. In the common memory mode, the computer host can choose to read card information service (CIS) bytes internally or externally. The interface logic block has, (a) a first external pin used either for a common memory chip select (CMCS) signal in the common memory mode or for an audio-in (AudIn) signal for the audio mode, (b) a second external pin used either for a common memory write (CMWR) signal in the common memory mode or for an audio-out (AudOut) signal in the audio mode, (c) a plurality of registers, (d) a logic circuit coupled to the registers, and (e) a microcontroller which can enable or disable the common memory write operation.

Abstract: A data transmission system for a host computer includes a converter coupled to the host computer and an external data transmission network for converting signals from one form into another, and an isolation circuit for electrically isolating the host computer from the data transmission network. The isolation circuit is placed between the host computer and the converter such that the host computer is electrically isolated from the data transmission network when data transmission is conducted between the host computer and the data transmission network. The isolation circuit digitally isolates the host computer from the external data transmission network such that noise and signal distortion generated by the isolation circuit do not affect the data transmission between the host computer and the data transmission network.