Abstract: A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level.

Abstract: A method for minimizing the time skew between signals traveling through various multi-cycle path nets linking one or several VLSI packages that includes a plurality of IC chips interconnected to each other. The method includes equalizing differences between the early and the late mode slack for each of the multi-cycle nets to decrease the joint probability of failure; maximizing the time balance between the early and the late mode slack; balancing over all the nets the difference between the early and the late mode slack, minimizing in the process statistical variations within the mode slack pair; and compensating for asymmetries between rising and falling switching times using the mode slack pair. The method allows multi-cycle path nets have their transmission line length confined between a maximum and a minimum length, which in turn minimizes the skew between signals in each of the nets, decreases cycle time and .improves the overall performance of the system.