Patents by Inventor Michael A. Heffner

Michael A. Heffner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7761739
    Abstract: Concurrent checkpointing for rollback recovery for system failures is disclosed. The system includes a stable database, and a processor configured to receive and process a checkpoint request while a first thread performs a process and a second thread stores contents of memory regions listed in a first list to the stable storage. Processing the checkpoint request includes write protecting all memory regions listed in a previously initialized and populated second list, initializing an empty third list, creating a coalesced list by combining the contents of the first and second lists, and assigning the coalesced list to the second thread while the first thread proceeds with the process.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: July 20, 2010
    Assignee: Librato, Inc.
    Inventors: Joseph F. Ruscio, Michael A. Heffner
  • Publication number: 20070220355
    Abstract: A method of identifying the source of a memory corruption error during operation of a checkpoint library includes receiving an error detection request and, in response to the request, write protecting all memory regions allocated to a checkpoint library. The method further includes detecting when a memory region is accessed for modification during operation of the checkpoint library and, in response to the detection, identifying the source of a memory corruption error affecting the memory region.
    Type: Application
    Filed: November 22, 2006
    Publication date: September 20, 2007
    Inventors: Joseph F. Ruscio, Michael A. Heffner
  • Publication number: 20070220356
    Abstract: Concurrent checkpointing for rollback recovery for system failures is disclosed. The system includes a stable database, and a processor configured to receive and process a checkpoint request while a first thread performs a process and a second thread stores contents of memory regions listed in a first list to the stable storage. Processing the checkpoint request includes write protecting all memory regions listed in a previously initialized and populated second list, initializing an empty third list, creating a coalesced list by combining the contents of the first and second lists, and assigning the coalesced list to the second thread while the first thread proceeds with the process.
    Type: Application
    Filed: November 22, 2006
    Publication date: September 20, 2007
    Inventors: Joseph F. Ruscio, Michael A. Heffner