Patents by Inventor Michael A. Howard

Michael A. Howard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6701482
    Abstract: A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≧8, N≧4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 2, 2004
    Assignee: Qualcomm Incorporated
    Inventors: Rohan S. Salvi, Michael A. Howard
  • Publication number: 20040037354
    Abstract: Method for optimizing an equalizer at a receiver in a communication system by training virtual parallel equalizers. Multiple configurations are applied for training an equalizer, and a performance measurement or estimate determined. The performance measures of the multiple configurations are compared to determine the optimum configuration. The training and selection are performed at a rate sufficiently higher than the received sample rate as to allow optimization in between processing of data samples.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 26, 2004
    Inventors: Srikant Jayaraman, Ivan Jesus Fernandez Corbaton, John E. Smee, Michael A. Howard
  • Publication number: 20030140304
    Abstract: A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.
    Type: Application
    Filed: December 14, 2001
    Publication date: July 24, 2003
    Inventors: James Y. Hurt, Michael A. Howard, Robert J. Fuchs
  • Publication number: 20030123526
    Abstract: Techniques to adjust the phase rotation of a modulated signal to compensate for the phase rotation introduced by circuit elements associated with the transmit signal path. In one implementation, at least one control signal is received, with each control signal being provided to adjust a particular characteristic (e.g., gain, bias current) of one or more circuit elements (e.g., VGA, PA) associated with the transmit signal path. The circuit elements can be located directly in, or operatively coupled to, the transmit signal path. A phase rotation corresponding to an operating state defined by the received control signal(s) is then determined, and the phase of the modulated signal is rotated by an amount related to the determined phase rotation. The phase rotation compensation can be performed at various locations along the transmit signal path by rotating either the data, the PN sequences used to spectrally spread the data, or the carrier signals used to modulate the data.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 3, 2003
    Inventors: Michael A. Howard, Peter J. Black
  • Publication number: 20030101401
    Abstract: A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≧8, N≧4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.
    Type: Application
    Filed: September 20, 2001
    Publication date: May 29, 2003
    Inventors: Rohan S. Salvi, Michael A. Howard
  • Patent number: 5539932
    Abstract: An adjustable length garment, for adjusting the length of a pant leg having an interior surface and a bottom edge, comprising an adjustment tab mounted to the interior surface near the bottom edge, and an adjustment array located above the adjustment tab on the interior surface. The adjustment array comprises a vertical strip having an inner seam and an outer seam along which the vertical strip is attached to the interior surface. The adjustment array also comprises fingers attached to the vertical strip along the inner seam, the fingers having type two fastener material. The adjustment tab has type two fastener material, and the vertical strip has type one fastener material for mating with the adjustment tab. The fingers can fold along the inner seam to affix to the vertical strip to cover exposed fastener material.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: July 30, 1996
    Inventor: Michael A. Howard
  • Patent number: 5535453
    Abstract: An adjustable length garment, for adjusting the length of a pant leg having an interior surface and a bottom edge, comprising an adjustment mechanism mounted to the interior surface near the bottom edge. The adjustment mechanism comprises an upper adjustment array and a lower adjustment array near the bottom edge. The adjustment mechanism comprises a vertical strip having an inner seam and an outer seam along which the vertical strip is attached to the interior surface. The adjustment mechanism also comprises fingers attached to the vertical strip along the inner seam, the fingers having integral hook and loop fastener material. The vertical strip has integral hook and loop fastener material for mating the upper adjustment array with the lower adjustment array. The fingers can fold along the inner seam to affix to the vertical strip to cover exposed fastener material.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: July 16, 1996
    Inventor: Michael A. Howard
  • Patent number: D403137
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 29, 1998
    Inventor: Michael A. Howard