Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

Abstract: A technique to dynamically enable or disable a number of stacks within a processor based on demand. At least one embodiment includes logic to detect whether a stack is needed and to enable the stack in response thereto and to disable the stack if it no longer needed.

Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.

Abstract: A method and apparatus for fast unsigned integral division, utilized in compositing images, sounds or other data, is provided. Compositing utilizes a division step. The divisor is the value of two to the Nth power minus one. The division comprises the steps of making a copy of the first number, thus producing a third number. The first number is shifted to the right by N. The third number is biased, and is then added to the first number. The resultant number is shifted right by N. This process results in a division by 2.sup.N -1, with short latency instructions, instead of the long latency instructions usually used for division operations.

Abstract: The present invention provides a method, in a computer system, for compressing bit formats provided in a first packed data sequence. One embodiment of the method comprises the steps of generating, in response to execution of a first instruction, a second packed data sequence by copying the first packed data sequence. A second step of replacing, in response to execution of a second instruction, a first portion of the second packed data sequence with a second portion of the second packed data sequence. A third step of generating, in response to execution of a third instruction, an intermediate result, by multiplying data elements of the first packed data sequence with corresponding data elements of a third packed data sequence, and adding adjacent products. A fourth step of performing, in response to execution of a fourth instruction, a first shift operation, wherein bits of the second packed data sequence are shifted.

Abstract: A method for computing a decimation-in-time Fast Fourier Transform of a sample is provided, the method including inputting first 2B-bit values representing the sample into a radix-4 first section of the decimation-in-time Fast Fourier Transform and performing first complex 2B-bit integer additions and subtractions on the first 2B-bit values to form second 2B-bit values, without performing a multiplication. The method also includes rounding the second 2B-bit values to form B-bit values output from the radix-4 first section of the decimation-in-time Fast Fourier Transform.