Patents by Inventor Michael A. Karls

Michael A. Karls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INSTRUCTION TO CANCEL OUTSTANDING CACHE PREFETCHES
    Publication number: 20180365156
    Abstract: Techniques relate to handling outstanding cache miss prefetches. A processor pipeline recognizes that a prefetch cancelling instruction is being executed. In response to recognizing that the prefetch cancelling instruction is being executed, all outstanding prefetches are evaluated according to a criterion as set forth by the prefetch cancelling instruction in order to select qualified prefetches. In response to evaluating, a cache subsystem is communicated with to cause cancelling of the qualified prefetches that fit the criterion. In response to successful cancelling of the qualified prefetches, a local cache is prevented from being updated from the qualified prefetches.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 20, 2018
    Inventors: Michael Karl GSCHWIND, Maged M. MICHAEL, Valentina SALAPURA, Eric M. SCHWARZ, Chung-Lung K. SHUM
  • Transactional execution processor having a co-processor accelerator, both sharing a higher level cache
    Patent number: 10157131
    Abstract: A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The higher level cache is shared with two or more processors. A processor may have a corresponding accelerator that performs operations on behalf of the processor. Transaction indicators are set in the higher level cache corresponding to the cache lines being accessed. The transaction aborts if a memory conflict with the transaction's cache lines from another transaction is detected, and the corresponding cache lines are invalidated. For a successfully completing transaction, the corresponding cache lines are committed and the data from store operations is stored.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum
  • Speculation control for improving transaction success rate, and instruction therefor
    Patent number: 10152418
    Abstract: Throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory is provided. Included is executing, by the processor, instructions of a transaction comprising determining whether the transaction is in throttling mode and based on the transaction being in throttling mode, executing memory instructions in-program-order. Also included is based on the transaction not-being in throttling mode, executing memory instructions out-of-program order.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Deferred response to a prefetch request
    Patent number: 10152419
    Abstract: Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor. Determining whether the prefetch request conflicts with a transaction of the local processor. Responding to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction of the local processor, by providing a requested prefetch data. Responding to a determination that the prefetch request conflicts with a transaction of the local processor by determining an evaluation of the prefetch request. Performing at least one of i) an abort of the prefetch request, ii) a quiesce the prefetch request, iii) a delay in the processing of the prefetch request for a delay period, and iv) an execution of the prefetch request based on the evaluation the prefetch request.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • HEARING ASSISTANCE SYSTEM INCORPORATING DIRECTIONAL MICROPHONE CUSTOMIZATION
    Publication number: 20180352343
    Abstract: A hearing assistance system comprises a left ear device and a right ear device respectively configured to be worn by a wearer. One or more microphones are provided at each of the left and right ear devices. One or more positional sensors are configured to determine a three-dimensional position of the hearing assistance system in response to the wearer looking at a sound source in space. A user interface is configured to receive an input directly from the wearer. A memory is configured to store the three-dimensional position of the hearing assistance system in response to the received input. A processor is configured to adjust a directional polar pattern of the one or more microphones provided at one or both of the left and right ear devices in response to the stored three-dimensional position.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 6, 2018
    Inventors: Karrie LaRae Recker, Michael Karl Sacha
  • CONTROLLING TENANT SERVICES BASED ON TENANT RANK
    Publication number: 20180348715
    Abstract: A control system controls tenant services to various tenants by obtaining tenant attributes for each tenant, with respect to a particular workload. A model is generated that models tenant usage performance for a set of best performing tenants. The model is then applied to a remainder of the tenants to obtain a metric indicative of a likely tenant capacity for incremental usage of the workload. The control system controls the services provided to the tenant based upon the likelihood of adoption metric.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Ravikumar Venkata Seetharama BANDARU, Michael Karl-Frans Berg
  • Power system utilizing processor core performance state control
    Patent number: 10146289
    Abstract: An information handling system includes a power supply coupled to a processor that includes a plurality of cores. A power system controller is coupled to the power supply and the processor. The power system controller may set each of the plurality of cores to a performance state that is below a highest performance state. The power system controller may then determine whether the power supplied from the power supply to the processor during operation is sufficient to operate each of the plurality of cores at the highest performance state. In response to the power being insufficient to operate each of the plurality of cores at the highest performance state, the power system controller may control the plurality of cores such that a subset operate at the highest performance state and the remainder operate at a performance state that is lower than the highest performance state.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 4, 2018
    Assignee: Dell Products L.P.
    Inventors: Mukund P. Khatri, Paul T. Artman, Humayun Khalid, Michael Karl Molloy
  • Deferred response to a prefetch request
    Patent number: 10146692
    Abstract: Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor. Determining whether the prefetch request conflicts with a transaction of the local processor. Responding to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction of the local processor, by providing a requested prefetch data. Responding to a determination that the prefetch request conflicts with a transaction of the local processor by determining an evaluation of the prefetch request. Performing at least one of i) an abort of the prefetch request, ii) a quiesce the prefetch request, iii) a delay in the processing of the prefetch request for a delay period, and iv) an execution of the prefetch request based on the evaluation the prefetch request.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Linking Optimized Entry Points for Local-Use-Only Function Pointers
    Publication number: 20180329699
    Abstract: Embodiments relate to using a local entry point with an indirect call function. More specifically, a linker is provided to generate at application modules that at least partially defines an indirect function call configuration. The linker loads a first address of a function by using a first symbolic reference, and determines that the function pointer value of the first symbolic reference is solely used to perform indirect calls in the same application module, e.g. local-use-only. The linker indicates that the first symbolic reference can be resolved using the local entry point associated with the function, and performs that indirect function call exclusively through the first symbolic reference, thereby reducing execution of operations.
    Type: Application
    Filed: July 19, 2018
    Publication date: November 15, 2018
    Applicant: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • FIXED DEPTH SKIN FLAP ELEVATOR DEVICE AND A METHOD OF USING THE SAME
    Publication number: 20180325542
    Abstract: A fixed depth skin flap elevator device is provided. The device includes an elongated handle having a proximal end and a distal end. The device further includes an upper arm and lower arm mounted to, so as to extend longitudinally from, the distal end of the handle. The upper arm overlays the lower arm. At least free ends of the upper and lower arms are spaced apart by a distance which is equal to a pre-determined cutting depth. A blade is supported on the lower arm at about its free end. Translation of at least the lower arm within a tissue interior results in separation of a deeper tissue from a surface tissue at a pre-determined cutting depth to form an undermined skin and subcutaneous surface tissue flap of uniform thickness. A method of using the device is also provided.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Inventor: Stanley Michael Karl Valnicek
  • Memory performance when speculation control is enabled, and instruction therefor
    Patent number: 10127155
    Abstract: Throttling execution in a transaction operating in a processor configured to execute memory instructions out-of-program-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory. Included is executing instructions of a transaction. Also included is determining whether the transaction is in throttling mode and based on determining that a transaction is in throttling mode, executing memory instructions in-program-order and dynamically prefetching memory operands of memory instructions.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventor: Michael Karl Gschwind
  • Hybrid tracking of transaction read and write sets
    Patent number: 10120804
    Abstract: Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. The indication(s) are stored in cache. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Transactional memory coherence control
    Patent number: 10120803
    Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
  • Transactional memory coherence control
    Patent number: 10120802
    Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
  • Compiling Optimized Entry Points for Local-Use-Only Function Pointers
    Publication number: 20180314504
    Abstract: Embodiments relate to using a local entry point with an indirect call function. A compiler is provided to determine and indicate in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module, e.g. local-use-only. The compiler loads an address of a function through use of a symbolic reference. When the compiler determines that the value employed by the symbolic reference is used exclusively to perform an indirect function call, the compiler proceeds to resolve a local entry point address of the function, thereby reducing a quantity of operations to be executed.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Applicant: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Detecting cache conflicts by utilizing logical address comparisons in a transactional memory
    Patent number: 10114752
    Abstract: A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Compiling optimized entry points for local-use-only function pointers
    Patent number: 10108404
    Abstract: Embodiments relate to using a local entry point with an indirect call function. More specifically, an indirect call function configuration comprises a first application module having a target function of the indirect function call, a second application module with a symbolic reference to the target function of the indirect function call, and a third application module to originate an indirect function call. A compiler is provided to determine and indicate in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module, e.g. local-use-only. A linker or loader can read the indication the compiler made in the program code. The linker or loader use the local entry point associated with the target function if the target function is defined in the same module as the reference and is local-use-only.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Loading optimized local entry points for local-use-only function pointers
    Patent number: 10108407
    Abstract: Embodiments relate to using a local entry point with an indirect call function. More specifically, an indirect call function configuration comprises a first application module having a target function of the indirect function call, a second application module with a symbolic reference to the target function of the indirect function call, and a third application module to originate an indirect function call. A compiler is provided to determine and indicate in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module, e.g. local-use-only. A linker or loader can read the indication the compiler made in the program code. The linker or loader use the local entry point associated with the target function if the target function is defined in the same module as the reference and is local-use-only.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Linking optimized entry points for local-use-only function pointers
    Patent number: 10108406
    Abstract: Embodiments relate to using a local entry point with an indirect call function. More specifically, an indirect call function configuration comprises a first application module having a target function of the indirect function call, a second application module with a symbolic reference to the target function of the indirect function call, and a third application module to originate an indirect function call. A compiler is provided to determine and indicate in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module, e.g. local-use-only. A linker or loader can read the indication the compiler made in the program code. The linker or loader use the local entry point associated with the target function if the target function is defined in the same module as the reference and is local-use-only.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • PREFETCH INSENSITIVE TRANSACTIONAL MEMORY
    Publication number: 20180300232
    Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the remote processor is greater than priority of the local processor by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.
    Type: Application
    Filed: June 22, 2018
    Publication date: October 18, 2018
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel