Abstract: A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.

Abstract: Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InxAl1-xN), InxGa1-xN, AlxGa1-xN, InxAlyGa1-x-yN, where (0<x?1, 0<y?1, 0<x+y?1).

Abstract: Light controlled switching modules are provide. In embodiments, a light controlled switching module includes: a housing; a light controlled semiconductor switch mounted to the housing, the light controlled semiconductor switch including a semiconductor body; at least one light source mounted to the housing in a spaced relationship from the light controlled semiconductor switch and positioned to direct light emitted from the at least one light source toward the semiconductor body; and first and second electrodes mounted to the housing and connected to the light controlled semiconductor switch, wherein the first and second electrodes are configured to have variable resistance between the first and the second electrode.

Abstract: A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.

Abstract: Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AIN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InxAl1-xN), InxGa1-xN, AlxGa1-xN, InxAlyGa1-x-yN, where (0<x?1, 0<y?1, 0<x+y?1).

Abstract: Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InxAl1-xN), InxGa1-xN, AlxGa1-xN, InxAlyGa1-x-yN, where (0<x?1, 0<y?1, 0<x+y?1).

Abstract: A computer-implemented method for evaluating a semiconductor wafer. In accordance with the present invention, using a properly designed neural network, the computer can take image data regarding the wafer at issue, plus image and electrical data regarding a prior wafer and devices fabricated on the prior wafer, to find relations to and between structural features, both known and previously unidentified, that can degrade the performance of devices fabricated on the wafer and/or can reduce the device yield of the wafer.

Abstract: A hyperbolic metamaterial assembly comprising alternating one or more first layers and one or more second layers forming a hyperbolic metamaterial, the one or more first layers comprising an intrinsic or non-degenerate extrinsic semiconductor and the one or more second layers comprising a two-dimensional electron or hole gas, wherein one of in-plane or out-of-plane permittivity of the hyperbolic metamaterial assembly is negative and the other is positive.

Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.

Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.

Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.

Abstract: A hyperbolic metamaterial assembly comprising alternating one or more first layers and one or more second layers forming a hyperbolic metamaterial, the one or more first layers comprising an intrinsic or non-degenerate extrinsic semiconductor and the one or more second layers comprising a two-dimensional electron or hole gas, wherein one of in-plane or out-of-plane permittivity of the hyperbolic metamaterial assembly is negative and the other is positive.

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract: A device with complementary non-inverted N-channel and inverted P-channel field effect transistors comprising a layer grown epitaxially on a substrate, a barrier layer, a two-dimensional electron gas in the first III-Nitride epitaxial layer, a second III-Nitride material layer, and a two-dimensional hole gas in the second III-Nitride epitaxial layer. A device with complementary inverted N-channel and non-inverted P-channel field effect transistors comprising a nitrogen-polar III-Nitride layer grown epitaxially, a barrier material layer, a two-dimensional hole gas, and a two-dimensional electron gas in the second III-Nitride epitaxial layer. A method of making complementary inverted P-channel and non-inverted N-channel III-Nitride field effect transistors. A method of making a complementary non-inverted P-channel field effect transistor and inverted N-channel III-Nitride field effect transistor on a substrate.

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract: A device with complementary non-inverted N-channel and inverted P-channel field effect transistors comprising a layer grown epitaxially on a substrate, a barrier layer, a two-dimensional electron gas in the first III-Nitride epitaxial layer, a second III-Nitride material layer, and a two-dimensional hole gas in the second III-Nitride epitaxial layer. A device with complementary inverted N-channel and non-inverted P-channel field effect transistors comprising a nitrogen-polar III-Nitride layer grown epitaxially, a barrier material layer, a two-dimensional hole gas, and a two-dimensional electron gas in the second III-Nitride epitaxial layer. A method of making complementary inverted P-channel and non-inverted N-channel III-Nitride field effect transistors. A method of making a complementary non-inverted P-channel field effect transistor and inverted N-channel III-Nitride field effect transistor on a substrate.

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract: A light emitting device having an electrically conductive metal foam or porous metal substrate, one or more light emitting nanowires in contact with the substrate, and a metal or conductive oxide contact layer in contact with each nanowire junction opposite of the substrate. More specifically, a light emitting device having an electrically conductive metal foam substrate, one or more light emitting nanowires in contact with the substrate, a quantum well on the nanowire(s), a p-type shell on the quantum well, a metal or conductive oxide contact layer in contact with the shell, and an energy down-converting material. Also disclosed is the related method of making a light emitting device.