Patents by Inventor Michael A. Maxim

Michael A. Maxim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230008701
    Abstract: One example method includes facilitating communications between a plurality of participants in a main meeting of a video conference, the communications encrypted using a first encryption key, the video conference provider lacking access to the first encryption key and a first decryption key; in response to receiving a command from a host to establish one or more sub-meetings, establishing the sub-meetings; for each sub-meeting, selecting a sub-meeting host; transmitting an indication that the selected sub-meeting host is a sub-meeting host; in response to receiving a request from a first participant to join a first sub-meeting, joining the first participant to the first sub-meeting; and facilitating sub-meeting communications between the sub-meeting host and the first participant, the sub-meeting communications encrypted using second encryption and decryption keys, the second encryption and decryption keys different than the first encryption and decryption keys, the video conference provider lacking access to
    Type: Application
    Filed: June 14, 2022
    Publication date: January 12, 2023
    Applicant: Zoom Video Communications, Inc.
    Inventor: Michael MAXIM
  • Patent number: 11394924
    Abstract: One example method includes facilitating communications between a plurality of participants in a main meeting of a video conference, the communications encrypted using a first encryption key, the video conference provider lacking access to the first encryption key and a first decryption key; in response to receiving a command from a host to establish one or more sub-meetings, establishing the sub-meetings; for each sub-meeting, selecting a sub-meeting host; transmitting an indication that the selected sub-meeting host is a sub-meeting host; in response to receiving a request from a first participant to join a first sub-meeting, joining the first participant to the first sub-meeting; and facilitating sub-meeting communications between the sub-meeting host and the first participant, the sub-meeting communications encrypted using second encryption and decryption keys, the second encryption and decryption keys different than the first encryption and decryption keys, the video conference provider lacking access to
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: July 19, 2022
    Assignee: Zoom Video Communications, Inc.
    Inventor: Michael Maxim
  • Publication number: 20120162622
    Abstract: Techniques are provided for efficient lithography processing and wafer layout. In particular, the techniques can be used to reduce the number of sacrificial exposures along the wafer perimeter region. In one example embodiment, an exposure system reticle is configured with both a normal area (die yielding area) and a dumification area (non-yielding area at wafer perimeter), thereby allowing for lithographic processing in the non-yielding areas sufficient to facilitate successful processing in the adjacent die yielding areas, but without requiring additional sacrificial exposures. This reduction in sacrificial exposures translates to a significant improvement in fab capacity. The techniques can be implemented, for example, on any number of lithography tools having an adjustable reticle or reticle blind capability and in the context of any technology nodes, such as 95 nm and smaller. The lithography tool may produce wafers at a faster rate.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventors: Alejandro Varela, Michael A. Maxim, Daniel E. Vanlare, Adi Lazar
  • Patent number: 6771011
    Abstract: Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventors: Michael A. Maxim, Oleh Karpenko, Farshid Adibi-rizi, Brett E. Huff
  • Publication number: 20030146682
    Abstract: Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
    Type: Application
    Filed: March 7, 2003
    Publication date: August 7, 2003
    Inventors: Michael A. Maxim, Oleh Karpenko, Farshid Adibi-rizi, Brett E. Huff
  • Patent number: 6572425
    Abstract: Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: June 3, 2003
    Assignee: Intel Corporation
    Inventors: Michael A. Maxim, Oleh Karpenko, Farshid Adibi-rizi, Brett E. Huff
  • Publication number: 20020140335
    Abstract: Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Inventors: Michael A. Maxim, Oleh Karpenko, Farshid Adibi-rizi, Brett E. Huff
  • Patent number: 6087733
    Abstract: A method and apparatus for compensating for the effects of nonuniform planarization in chemical-mechanical polishing (CMP) such as the erosion occurring from the removal of titanium nitride/tungsten films is disclosed. In the context of alignment marks, dummy marks are disposed on both sides of the actual alignment marks providing a similar feature density as the alignment marks. During the CMP, the dummy marks reside in the area of nonuniform erosion, leaving the actual marks in an area of uniform erosion. The present invention may also be used to control underlayer erosion variations in the high feature density device areas adjacent to the low feature density open areas by providing dummy features in the low feature density areas.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventors: Michael A. Maxim, Michael Kocsis, Ning Hsieh, Matthew Prince, Kenneth C. Cadien
  • Patent number: D376946
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: December 31, 1996
    Inventor: Michael Maxim