Abstract: Described herein are systems and methods for assessing a biological sample. The methods include: characterizing a speckled pattern to be applied by a diffuser; positioning a biological sample relative to at least one coherent light source such that at least one coherent light source illuminates the biological sample; diffusing light produced by the at least one coherent light source; capturing a plurality of illuminated images with the embedded speckle pattern of the biological sample based on the diffused light; iteratively reconstructing the plurality of speckled illuminated images of the biological sample to recover an image stack of reconstructed images; stitching together each image in the image stack to create a whole slide image, wherein each image of the image stack at least partially overlaps with a neighboring image; and identifying one or more features of the biological sample. The methods may be performed by a near-field Fourier Ptychographic system.

Abstract: A current reference circuit with one or more current mirror devices having dynamic body biasing includes a voltage-to-current converter circuit having a feedback loop that includes an operational amplifier, an NMOS device, and a resistor to generate a reference current; a current mirror circuit, including one or more current mirror devices with source degeneration, to produce one or more output currents that are copies of the reference current; and a body-biasing stage including an active N-well to dynamically set a body-biasing voltage for the one or more current mirror devices.

Abstract: A dual loop regulated switched-capacitor converter circuit includes a switched capacitor array that includes a plurality of switches and capacitors; a digital controller for controlling the switched capacitor array; a pulse modulator connected to the digital controller; a clock generator connected to the digital controller; a first comparator connected to the pulse modulator; and a feedback network connected to the first comparator.

Abstract: A dental solution dispenser includes a body having a first end, a second end, and including a front housing at the first end, a twist back at the second end, and a grip that interposes the front housing and the twist back. An applicator tip is coupled to the body at the first end, and an ampoule assembly is positioned within the body and includes an ampoule sealed at one end with a frangible seal and defining a fluid chamber for storing a dental solution. A mandrel extends longitudinally within the body and provides a piercing member. The twist back is rotatable relative to the grip to pierce the frangible seal with the piercing member. A trigger is coupled to the body and pivotable between an engaged position, where the trigger engages the ampoule assembly, and a disengaged position, where the trigger disengages the ampoule assembly.

Abstract: A dental solution dispenser includes a body having a first end, a second end, and including a front housing at the first end, a twist back at the second end, and a grip that interposes the front housing and the twist back. An applicator tip is coupled to the body at the first end, and an ampoule assembly is positioned within the body and includes an ampoule sealed at one end with a frangible seal and defining a fluid chamber for storing a dental solution. A mandrel extends longitudinally within the body and provides a piercing member. The twist back is rotatable relative to the grip to pierce the frangible seal with the piercing member. A trigger is coupled to the body and pivotable between an engaged position, where the trigger engages the ampoule assembly, and a disengaged position, where the trigger disengages the ampoule assembly.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract: A method for introducing biologically active molecules into animal or human cells using an electric current includes suspending the cells and dissolving the biologically active molecules in a buffer solution including HEPES and at least 10 mmol×1?1 magnesium ions (Mg2+), the buffer solution having a buffer capacity of at least 20 mmol×1?1 ×pH?1 at a change in the pH from pH 7 to pH 8 and at a temperature of 25° C., and an ionic strength of at least 200 mmol×1?1. An electric voltage is applied to the suspension.