Abstract: A current reference circuit with one or more current mirror devices having dynamic body biasing includes a voltage-to-current converter circuit having a feedback loop that includes an operational amplifier, an NMOS device, and a resistor to generate a reference current; a current mirror circuit, including one or more current mirror devices with source degeneration, to produce one or more output currents that are copies of the reference current; and a body-biasing stage including an active N-well to dynamically set a body-biasing voltage for the one or more current mirror devices.

Abstract: A dual loop regulated switched-capacitor converter circuit includes a switched capacitor array that includes a plurality of switches and capacitors; a digital controller for controlling the switched capacitor array; a pulse modulator connected to the digital controller; a clock generator connected to the digital controller; a first comparator connected to the pulse modulator; and a feedback network connected to the first comparator.

Abstract: A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract: A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage.

Abstract: A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage.

Abstract: A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE) in a unified signaling system. An input data stream is sliced into an even data stream and an odd data stream, whereby the sliced data is compared to a programmable threshold depending upon a detection mode. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, a correct portion of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is summed in current mode with the feedback data and converted to voltage prior to sampling the currently received data bit.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.

Abstract: A method and apparatus for combining an alternating current (AC) coupling technique with a low frequency restoration technique to provide AC coupling with low frequency restoration of the attenuated low frequency content. The low frequency restoration circuit operates to extract low frequency information prior to being high-pass filtered by the AC coupling circuit. The low frequency restoration circuit then buffers the low frequency information through a low frequency restoration amplifier, applies a programmable common mode voltage to the buffered, low frequency information, and then restores the buffered, common mode adjusted, low frequency information to the output of the AC coupling circuit.

Abstract: An example embodiment is directed to an arrangement and method for phase-aligning digital data to be sent by transmit-data modules over respectively-situated serial links. A reference clock signal is communicatively coupled to each transmit-data module, each transmit-data module having a data driver and a clock circuit. At the serial links, each respective data driver sends digital data in response to a clock-output signal and a phase-adjusted clock-load signal that is used to load the data driver. The phase of the clock-load signal is adjusted relative to misalignment between the clock-load signal and the reference clock signal so that each data driver loads the digital data in a time-aligned manner for link transmission. The present invention is useful in applications involving programmable logic devices and other skew-susceptible parallel transmission arrangements.

Abstract: An example embodiment is directed to shifting the common mode voltage of an analog oscillation stage toward a center line between the upper and lower power-supply rails of a first digital circuit. The first digital circuit has a digital input port adapted to respond to signal transitions defined between the supply rails, and the analog oscillation stage generates an oscillating analog signal that has a common-mode voltage that is not centered between the upper and lower power-supply rails. The oscillating analog signal, which drives the digital input port, changes alternately with the phases of the oscillating analog signal. To shift the common mode voltage of an analog oscillation stage toward the center line between the rails, a feedback circuit generates a contending digital signal that drives the digital input port with alternating states as defined by opposite phases.

Abstract: A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero (“RTZ”) data latch register. The RTZ data latch register has a first (“even”) series of RTZ data latches and a second (“odd”) series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.

Abstract: A limiting circuit includes an input transconductance stage, an output transconductance stage, a feedback transconductance stage, first and second resistive loads, and a level limiting circuit. The input transconductance stage is operably coupled to convert an input voltage signal into an input current signal. The first resistive load is operably coupled to convert the input current signal and a feedback current signal into an intermediate output voltage signal. The output transconductance stage is operably coupled to convert the intermediate output voltage signal into an output current signal. The second resistive load is operably coupled to convert the output current signal into an output voltage signal. The feedback transconductance stage is operably coupled to produce the feedback current signal based on the output voltage signal. The level limiting module is operably coupled to limit at least one voltage level of the feedback transconductance stage.

Abstract: A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first current-handling terminal connected to the first output terminal (Q), a second current-handling terminal connected to the second output terminal (Qb), and a first control terminal connected to a clock signal (C). A second transistor has a third current-handling terminal connected to the first output terminal (Q), a fourth current-handling terminal connected to the voltage supply terminal (Vss), and a second control terminal connected to a first input terminal (X1) of the output stage. A third transistor (440) has a fifth current-handling terminal connected to the first output terminal (Q), a sixth current-handling terminal connected to the voltage supply terminal (Vss), and a third control terminal connected to the second output terminal (Qb).