Abstract: Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.

Abstract: One embodiment sets forth a technique for performing one or more matrix multiplication operations based on a first matrix and a second matrix. The technique includes receiving data associated with the first matrix from a first traversal engine that accesses nonzero elements included in the first matrix via a first tree structure. The technique also includes performing one or more computations on the data associated with the first matrix and the data associated with the second matrix to produce a plurality of partial results. The technique further includes combining the plurality of partial results into one or more intermediate results and storing the one or more intermediate results in a first buffer memory.

Abstract: A system and method for providing zone-specific media to a user. As a non-limiting example, various aspects of this disclosure provide a system and method that flexibly selects and provides media content (e.g., audio content), where such content is selected based, at least in part, on a user location (e.g., location within a premises).

Abstract: A method of applying a coating composition to a substrate utilizing a high transfer efficiency applicator include the steps of providing the high transfer efficiency applicator comprising an array of nozzles wherein each nozzle defines a nozzle orifice having a diameter of from 0.00002 m to 0.0004, providing the coating composition, and applying the coating composition to the substrate through the nozzle orifice without atomization such that at least 99.9% of the applied coating composition contacts the substrate to form a coating layer having a wet thickness of at least 5 microns, wherein the coating composition includes a carrier, a binder, and a radar reflective pigment or a LiDAR reflective pigment. The coating composition has an Ohnesorge number (Oh) of from about 0.01 to about 12.6, a Reynolds number (Re) of from about 0.02 to about 6,200, and a Deborah number (De) of from greater than 0 to about 1730.

Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

Abstract: The present teachings contemplate a method comprising coating an polymeric material with a composition including a dicarbonyl compound and having a viscosity of from about 50 cps to about 500 cps, wherein the coating initiates either: (i) spontaneous polymerization (e.g., in less than about one minute) at room temperature of the composition without the addition of an initiator; or (ii) polymerization at room temperature at a selected later time with or without the addition of an initiator; and wherein the composition adheres or facilitates adhesion of the polymeric material to a substrate.

Abstract: An initiating processing tile generates an offload request that may include a processing tile ID, source data needed for the computation, program counter, and destination location where the computation result is stored. The offload processing tile may execute the offloaded computation. Alternatively, the offload processing tile may deny the offload request based on congestion criteria. The congestion criteria may include a processing workload measure, whether a resource needed to perform the computation is available, and an offload request buffer fullness. In an embodiment, the denial message that is returned to the initiating processing tile may include the data needed to perform the computation (read from the local memory of the offload processing tile). Returning the data with the denial message results in the same inter-processing tile traffic that would occur if no attempt to offload the computation were initiated.

Abstract: A coating composition for application to a substrate utilizing a high transfer efficiency applicator. The coating composition includes a carrier, a binder, a corrosion inhibiting pigment. The coating composition has an Ohnesorge number (Oh) of from about 0.01 to about 12.6. The coating composition has a Reynolds number (Re) of from about 0.02 to about 6,200. The coating composition has a Deborah number (De) of from greater than 0 to about 1730.

Abstract: Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.

Abstract: A balun is enhanced with design features that extend the operational bandwidth of the balun allowing the balun to operate at lower frequencies. The design enhancements also suppress resonances that otherwise cause sudden power drops at a resonance frequency while a load is connected between the balun's differential outputs.

Abstract: Intelligent voice response systems and methods may include one or more machine readable instructions stored in a memory that cause a processor to receive an automated input including at least two of the following: a vehicle metric of the vehicle, a driving score of a user of the vehicle, a driving time during a trip of the vehicle, a geographical location of the vehicle, an adverse weather event within a predetermined distance of the vehicle, a historical driving route of the vehicle, a predicted driving route of the vehicle within a first predetermined period of time, or a sound within a predetermined distance of the vehicle. An action may be generated and implemented and reception of an affirmative response from the user may be determined. An alert may be generated to the user based on the affirmative response.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.

Abstract: Aspects of the subject disclosure may include, for example, a database being maintained that has information indicating states of network resources, which can be determined based on physical activities, logical activities and hybrid activities performed on or by the network resources; obtaining activity information for a particular network resource, where the activity information is a physical activity, a logical activity and/or a hybrid activity; and determining whether a state change for the particular network resource should be made such as to whether the activity information corresponds to and warrants change to at least one of an inventory state, an operational state, or a detailed state. Other embodiments are disclosed.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: Intelligent voice response systems and methods may include one or more machine readable instructions stored in a memory that cause a processor to receive an automated input including at least two of the following: a vehicle metric of the vehicle, a driving score of a user of the vehicle, a driving time during a trip of the vehicle, a geographical location of the vehicle, an adverse weather event within a predetermined distance of the vehicle, a historical driving route of the vehicle, a predicted driving route of the vehicle within a first predetermined period of time, or a sound within a predetermined distance of the vehicle. An action may be generated and implemented and reception of an affirmative response from the user may be determined. An alert may be generated to the user based on the affirmative response.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel that includes memory accesses for prefetching data for a processing kernel into a memory, and, subsequent to executing at least a portion of the prefetch kernel, executing the processing kernel where the processing kernel includes accesses to data that is stored into the memory resulting from execution of the prefetch kernel.