Patents by Inventor Michael A. Parker

Michael A. Parker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11736402
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Patent number: 11593619
    Abstract: A computer architecture for multiplier-less machine learning is disclosed. According to some aspects, a neural network apparatus include processing circuitry and memory. The processing circuitry accesses a plurality of weights for a neural network layer and an input vector for the neural network layer, the input vector comprising a plurality of data values. The processing circuitry provides the plurality of weights and the input vector to an addition layer. The addition layer generates data value-weight pairs and, for each data value-weight pair, creates an input block comprising a sum of the data value and the weight. The processing circuitry sorts the input blocks generated by the addition layer. The processing circuitry cancels any opposite signed input blocks from the sorted input blocks to generate a set of blocks. The processing circuitry outputs a Kth largest value from the set of blocks. K is a positive integer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 28, 2023
    Assignee: Raytheon Company
    Inventor: Michael A. Parker
  • Patent number: 11528229
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Patent number: 11477122
    Abstract: Technologies for improving throughput in a network include a node switch. The node switch is to obtain expected performance data indicative of an expected data transfer performance of the node switch. The node switch is also to obtain measured performance data indicative of a measured data transfer performance of the node switch, compare the measured performance data to the expected performance data to determine whether the measured data transfer performance satisfies the expected data transfer performance, determine, as a function of whether the measured data transfer performance satisfies the expected data transfer performance, whether to force a unit of data through a non-minimal path to a destination, and send, in response to a determination to force the unit of data to be sent through a non-minimal path, the unit of data to an output port of the node switch associated with the non-minimal path. Other embodiments are also described.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Timo Schneider, Michael A. Parker
  • Publication number: 20220141138
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Application
    Filed: October 13, 2021
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Publication number: 20220029839
    Abstract: Technologies for densely packaging network components for large scale indirect topologies include group of switches. The group of switches includes a stack of node switches that includes a first set of ports and a stack of global switches that includes a second set of ports. The stack of node switches are oriented orthogonally to the stack of global switches. Additionally, the first set of ports are oriented towards the second set of ports and the node switches are connected to the global switches through the first and second sets of ports. Other embodiments are also described and claimed.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Richard J. Dischler
  • Patent number: 11153211
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Patent number: 11153105
    Abstract: Technologies for densely packaging network components for large scale indirect topologies include group of switches. The group of switches includes a stack of node switches that includes a first set of ports and a stack of global switches that includes a second set of ports. The stack of node switches are oriented orthogonally to the stack of global switches. Additionally, the first set of ports are oriented towards the second set of ports and the node switches are connected to the global switches through the first and second sets of ports. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Richard J. Dischler
  • Patent number: 11095560
    Abstract: Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Gary Muntz, Robert Zak, Thomas Lovett, Michael A. Parker
  • Patent number: 11055247
    Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Gaspar Mora Porta, Michael A Parker, Roberto Penaranda Cebrian, Albert S Cheng, Francesc Guim Bernat
  • Patent number: 10951526
    Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Michael A. Parker
  • Publication number: 20210036959
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Application
    Filed: July 14, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: ALBERT S. CHENG, THOMAS D. LOVETT, MICHAEL A. PARKER
  • Patent number: 10911366
    Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Scott S. Diesing, Michael A. Parker, Albert S. Cheng, Nan Ni
  • Patent number: 10771404
    Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request message, wherein the request message includes a read trigger, an indicator selector, and a completion trigger, determine an indicator that relates to the indicator selector, and perform an action when the read trigger is activated.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: David Keppel, Thomas D. Lovett, Michael A. Parker, Robert C. Zak, Jr.
  • Patent number: 10757039
    Abstract: Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Patent number: 10715452
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Publication number: 20200134429
    Abstract: A computer architecture for multiplier-less machine learning is disclosed. According to some aspects, a neural network apparatus include processing circuitry and memory. The processing circuitry accesses a plurality of weights for a neural network layer and an input vector for the neural network layer, the input vector comprising a plurality of data values. The processing circuitry provides the plurality of weights and the input vector to an addition layer. The addition layer generates data value-weight pairs and, for each data value-weight pair, creates an input block comprising a sum of the data value and the weight. The processing circuitry sorts the input blocks generated by the addition layer. The processing circuitry cancels any opposite signed input blocks from the sorted input blocks to generate a set of blocks. The processing circuitry outputs a Kth largest value from the set of blocks. K is a positive integer.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventor: Michael A. Parker
  • Publication number: 20200050569
    Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 13, 2020
    Inventors: Gaspar MORA PORTA, Michael A PARKER, Roberto PENARANDA CEBRIAN, Albert S. CHENG, Francesc GUIM BERNAT
  • Patent number: 10394738
    Abstract: Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each include two or more first and second level switches in which each of the first level switches are communicatively coupled to each of the plurality of second level switches to form a complete bipartite graph. Additionally, each of the groups is interconnected to each of the other groups via a corresponding global link connecting a second level switch of one group to a corresponding second level switch of another group. Further, each of the first level switches are communicatively coupled to one or more computing nodes. Other embodiments are described herein.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Wayne A. Downer
  • Patent number: 10389636
    Abstract: Technologies for adaptive routing based on network traffic pattern characterization include a network switch configured to receive a network packet via one of a plurality of input ports and identify a set of the plurality of output ports associated with a path usable to forward the received network packet to a destination computing device along. The network switch is further configured to adjust a total congestion value for each of the set of output ports based on a type of the path to which each of the set of output ports corresponds and a value of a minimal path counter to which each of the set of output ports corresponds and enqueue the received network packet into an output buffer queue of one of the set of output ports based on the total congestion value. Other embodiments are described herein.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker