Abstract: Novel tools and techniques are provided for implementing blockchain transactions, and, more particularly, to methods, systems, and apparatuses for securing a blockchain with proof-of-transactions. In various embodiments, the blockchain system utilizes a proof-of-transactions approach that is based on a multi-player voting system and that is not susceptible to a free-rider problem that affects many other cryptocurrencies. The proof-of-transactions approach allows the cryptocurrency network to divide revenue between the nodes in the peer-to-peer network that provides bandwidth and connectivity and a set of other nodes that solve computational puzzles that safeguard the security of the blockchain system.

Abstract: Novel tools and techniques are provided for implementing blockchain transactions, and, more particularly, to methods, systems, and apparatuses for securing a blockchain with proof-of-transactions. In various embodiments, the blockchain system utilizes a proof-of-transactions approach that is based on a multi-player voting system and that is not susceptible to a free-rider problem that affects many other cryptocurrencies. The proof-of-transactions approach allows the cryptocurrency network to divide revenue between the nodes in the peer-to-peer network that provides bandwidth and connectivity and a set of other nodes that solve computational puzzles that safeguard the security of the blockchain system.

Abstract: Novel tools and techniques are provided for implementing blockchain transactions, and, more particularly, to methods, systems, and apparatuses for securing a blockchain with proof-of-transactions. In various embodiments, the blockchain system utilizes a proof-of-transactions approach that is based on a multi-player voting system and that is not susceptible to a free-rider problem that affects many other cryptocurrencies. The proof-of-transactions approach allows the cryptocurrency network to divide revenue between the nodes in the peer-to-peer network that provides bandwidth and connectivity and a set of other nodes that solve computational puzzles that safeguard the security of the blockchain system.

Abstract: Novel tools and techniques are provided for implementing blockchain transactions, and, more particularly, to methods, systems, and apparatuses for securing a blockchain with proof-of-transactions. In various embodiments, the blockchain system utilizes a proof-of-transactions approach that is based on a multi-player voting system and that is not susceptible to a free-rider problem that affects many other cryptocurrencies. The proof-of-transactions approach allows the cryptocurrency network to divide revenue between the nodes in the peer-to-peer network that provides bandwidth and connectivity and a set of other nodes that solve computational puzzles that safeguard the security of the blockchain system.

Abstract: A method includes, determining a target publication, identifying one or more content suggestions associated with the target publication, and causing a user to be prompted to input content. The input content satisfies at least a portion of the one or more content suggestions.

Abstract: A method includes, determining a target publication, identifying one or more content suggestions associated with the target publication, and causing a user to be prompted to input content. The input content satisfies at least a portion of the one or more content suggestions.

Abstract: A system generates visualizations representing publication data for one or more publications. The visualizations present information to support consumer decisions to read, submit, or otherwise interact with the publication. The visualizations may also assist in publisher or other curator decisions related to shaping the content of the publication. In some cases, the publication data may be derived from semantic analysis of the content of the publication or other related publications.

Abstract: A method includes, determining a target publication, identifying one or more content suggestions associated with the target publication, and causing a user to be prompted to input content. The input content satisfies at least a portion of the one or more content suggestions.

Abstract: In the presence of certain polyols, a guar gum or similar polysaccharide thickener solution is boron crosslinked before achievement of complete hydration of the thickener, without compromising the viscosity level achieved in a fracturing fluid by the time it is pumped into the wellbore and fractures the subterranean formation adjacent the wellbore. Methods continuously involve hydrating a polysaccharide thickener to an extent of 10% to 75%, but less than full hydration. Before 75% hydration is exceeded, a boron crosslinker is added. Upon addition of the boron crosslinker, the fluid is injected into the wellbore to stimulate hydrocarbon production. Because less time is needed for hydration, well site mixing equipment is down-sized smaller to achieve better efficiency and cost savings.

Abstract: Suspensions are provided of water-soluble materials in non-aqueous carrier fluids using suspension agents that include thixotropic agents and, optionally, organophilic clays. Methods of forming such suspensions are provided. Methods are also provided for using such suspensions to prepare aqueous solutions, in particular thickened aqueous solutions, in particular for use in oilfield treatments.

Abstract: A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than traditional static designs and, therefore, requires a smaller amount of integrated circuit layout area while nevertheless affording higher speed operating performance than that exhibited in existing conventional circuits.

Abstract: Suspensions are provided of water-soluble materials in non-aqueous carrier fluids using suspension agents that include organophilic clays. Methods of forming such suspensions are provided. Methods are also provided for using such suspensions to prepare aqueous solutions, in particular thickened aqueous solutions, in particular for use in oilfield treatments.

Abstract: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Abstract: A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and is capable of executing refreshes frequently enough to prevent data loss. Any subarray of the memory can be written from cache or refreshed at the same time any other subarray is read or written externally.

Abstract: A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.

Abstract: A precharge initiated dynamic random access memory (DRAM) technique of especial utility with respect to DRAM devices and other integrated circuit devices incorporating embedded DRAM in which the rising edge of each clock initiates a precharge to those subarrays that were active as opposed to conventional techniques wherein the subarrays are typically precharged so that they are made ready on the rising edge of the clock, which would then start an active cycle. The longer restore time that is achieved can be used to enable the establishment of better logic “1” and “0” levels in the memory cells, to reduce the device clock period and/or to enable other functions to be performed in parallel with the precharge function.

Abstract: A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.

Abstract: A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.

Abstract: A dual-port memory substantially eliminates noise problems associated with the staggered methods of operation. The first and second word lines of a dual-port memory cell are simultaneously activated, such that all four bit lines associated with the cell also move at the same time. The dual-port memory uses simple control logic circuitry without the need for additional external control signals. There are no lock-out times or write restrictions with the method of the present invention. The dual-port memory of the present invention includes a method for hiding refresh, and a method for increasing operating speed.

Abstract: Methods and compositions are disclosed for controlled addition of components that decrease the viscosity of the viscoelastic surfactant fluids or for controlled changes in the electrolyte concentration or composition of the viscoelastic surfactant fluids. One aspect of the invention relates to the use of internal breakers with a delayed activation. Another aspect of the invention relates to the use of precursors that release a breaking system such as alcohol by a process such as melting, slow dissolution, reaction with a compound present in the fluid or added to the fluid during or after the step of injecting, rupture of an encapsulating coating and de-adsorption of a breaking agent absorbed into solid particles. In another aspect of the invention, alcohols are included in a pad to reduce the low-shear viscosity and reduce the resistance to flow of the treatment fluids during a desired phase of the treatment.