Abstract: A method and system for trans-loading solid particulates from a hopper to a storage container, by clamping a trough to a discharge gate of the hopper, the trough having an open top, sides, and a bottom, a vacuum pipe extending into the trough, and at least one aerator located on the trough, to which is provided an aerating gas. The method further comprises at least partially evacuating the storage container to cause at least a partial vacuum therein and drawing a vacuum through a conveyor hose connected to the trough.

Abstract: A method and system for trans-loading solid particulates from a hopper to a storage container, by clamping a trough to a discharge gate of the hopper, the trough having an open top, sides, and a bottom, a vacuum pipe extending into the trough, and at least one aerator located on the trough, to which is provided an aerating gas. The method further comprises at least partially evacuating the storage container to cause at least a partial vacuum therein and drawing a vacuum through a conveyor hose connected to the trough.

Abstract: A method and system for trans-loading solid particulates from a hopper to a storage container, by clamping a trough (110) to a discharge gate of the hopper, the trough having an open top, sides, and a bottom, a vacuum pipe (140) extending into the trough, and at least one aerator (150) located on the trough, to which is provided an aerating gas. The method further comprises at least partially evacuating the storage container to cause at least a partial vacuum therein and drawing a vacuum through a conveyor hose connected to the trough.

Abstract: A method and system for trans-loading solid particulates from a hopper to a storage container, by clamping a trough (110) to a discharge gate of the hopper, the trough having an open top, sides, and a bottom, a vacuum pipe (140) extending into the trough, and at least one aerator (150) located on the trough, to which is provided an aerating gas. The method further comprises at least partially evacuating the storage container to cause at least a partial vacuum therein and drawing a vacuum through a conveyor hose connected to the trough.

Abstract: A system and method for dynamically reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for dynamically reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes, e.g., when changes occur to an IO configuration. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Abstract: A system and method for reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Abstract: Mechanisms for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Abstract: Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Abstract: In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Abstract: A system for reassigning root complex resources in a multi-root PCI express system identifies resources from a lower performing root complex port and reassigns those resources to the higher performing root complex. The system does not change the number of PCI Express lanes, the resources each root complex uses may be reassigned to allow those resources to be translated to available credits for an endpoint. For example, in one embodiment, two root complexes are configured as x8 root complexes with the root complex resources distributed across the two root complexes based upon the usage of the root complex resources.

Abstract: A system and method for reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Abstract: A system and method for dynamically reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for dynamically reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes, e.g., when changes occur to an IO configuration. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Abstract: A system and method for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Abstract: A system and method for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: In combination with a toilet paper dispenser having a base mountable upon a wall and a pair of opposed trunnion arms removably mounting a dowel which loosely journals a roll of toilet paper having a lead sheet. The improvement comprises in combination therewith a biasing means for restraining unwinding of the roll, including a cover projecting from the wall and overlying the roll. A mount strip of resilient material is secured to the cover and includes a depending hinge secured to the wall. A resilient friction tab projects from the mount strip and resiliently and tangentially and yieldably bears against the roll.