Patents by Inventor Michael A. Ruegg
Michael A. Ruegg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957400Abstract: A surgical device for examination and treatment of a target area. The surgical device includes a shaft portion that extends along a longitudinal axis and that is configured to be inserted into a patient's body, a surgical tool provided within the outer sheath and configured to be movable along the longitudinal axis, and an optical assembly provided at a distal end of the inner shaft, the optical assembly including a light source and an imaging sensor.Type: GrantFiled: April 26, 2023Date of Patent: April 16, 2024Assignee: American Endoscopic Innovations, LLCInventors: James Barry, Israel Franco, Michael Grasso, III, Thomas Ruegg
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Publication number: 20060169393Abstract: A method and apparatus for making a tire with a built in sealant is provided. The method includes the steps of mounting an inner liner onto a tire building drum, extruding a sealant composition into strips having tapered sidewalls, cutting the strip to a desired length, mounting the sealant over the inner liner, and layering one or more tire components over the sealant.Type: ApplicationFiled: December 22, 2005Publication date: August 3, 2006Inventors: Bina Botts, Michael Ruegg, Brandy Kohut, Warren Ripple
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Patent number: 6700722Abstract: A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality of clock pulse waves, each having substantially equal period and each being out of phase with respect to other clock pulse waves; an output including at least one output terminal corresponding to one of the clock pulse waves; and a zero phase circuit configured to sequentially couple the plurality of clock pulse waves to the corresponding output terminals.Type: GrantFiled: May 25, 2001Date of Patent: March 2, 2004Assignee: Infineon Technologies AGInventors: Michael A. Ruegg, Sasan Cyrusian
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Patent number: 6690525Abstract: A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant bit counter. The least-significant-bit counter is programmed to an initial state and configured to decrement a state with each pulse of a clock wave. The least-significant-bit counter provides an output signal when the least-significant-bit counter has a zero-count state. The most-significant-bit counter decrements when the least-significant-bit counter has a zero-count state and provides an output signal when the least-significant-bit counter has a zero-count state. A counter output pulse is generated and the high-speed counter is reset to the initial state when both the least-significant bit counter and the most-significant bit counter have a zero-count state.Type: GrantFiled: May 25, 2001Date of Patent: February 10, 2004Assignee: Infineon Technologies AGInventors: Michael A. Ruegg, Sasan Cyrusian
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Patent number: 6661590Abstract: A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).Type: GrantFiled: May 25, 2001Date of Patent: December 9, 2003Assignee: Infineon Technologies AGInventors: Sasan Cyrusian, Stephen J. Franck, Sriharsha Annadore, Elmar Bach, Siegfried Hart, Thomas Blon, William G. Bliss, James Wilson Rae, Michael Ruegg, Ulrich Huewels, Fritz Mistlberger
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Patent number: 6653879Abstract: An input signal is received having a period and an input pulse width. The input pulse width of an input signal is adjusted to an output pulse width of an output signal based upon a recording control signal for control of recording on a storage medium. The output signal and the output pulse width is derived from a triggering edge of a first selected signal of a first selected phase and a triggering edge of a second selected signal of a second selected phase in succession. The first selected signal and the second selected signal are selected from an assortment of reference signals that have distinct relative phases to provide the output pulse width of a desired duration. The number of distinct relative phases available for formation of the output pulse width is increased by one or more of the following: delaying, dividing, inverting, and interpolating one or more reference signals.Type: GrantFiled: May 25, 2001Date of Patent: November 25, 2003Assignee: Infineon Technologies AGInventors: Sasan Cyrusian, Michael A. Ruegg
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Patent number: 6512404Abstract: A low voltage charge pump for a phase locked loop is disclosed. The low voltage charge pump provides linear control for a voltage at a loop filter. The charge pump is supplied by a power supply between 1.6 and 2.0 V and is configured to provide linear charging and discharging of the loop filter to a potential between 150 mVolts to within 150 mVolts of the power supply voltage.Type: GrantFiled: May 25, 2001Date of Patent: January 28, 2003Assignee: Infineon Technologies AGInventors: Michael A. Ruegg, Sasan Cyrusian
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Patent number: 6501324Abstract: A high-speed multiplexer that includes a reduced number of components in the pull-up and/or the pull-down circuits operates faster than conventional multiplexers and can process higher frequency input signals. The pull-up circuit may be a singe p-type MOSFET transistor and the pull-down circuit may be a single n-type MOSFET transistor. The switching circuits may include transistor-based NOR gates. The multiplexer may have numerous channels, for example 2 to 256 or more channels.Type: GrantFiled: May 25, 2001Date of Patent: December 31, 2002Assignee: Infineon Technologies AGInventors: Michael Ruegg, Sasan Cyrusian
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Publication number: 20020176188Abstract: A offset cancellation of charge pump based phase detector is disclosed. The methods and circuits disclosed cancel inherent with a phase detector and imbalanced charge pumps. The offset cancellation includes detecting the phase detector and the charge pump offset with a calibration signal and a reference voltage source, and applying a calibration current to cancel the phase detector and charge pump offset.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies N.A. Inc.Inventors: Michael A. Ruegg, Sasan Cyrusian
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Publication number: 20020175723Abstract: A low voltage charge pump for a phase locked loop is disclosed. The low voltage charge pump provides linear control for a voltage at a loop filter. The charge pump is supplied by a power supply between 1.6 and 2.0V and is configured to provide linear charging and discharging of the loop filter to a potential between 150 mVolts to within 150 mVolts of the power supply voltage.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies N.A., Inc.Inventors: Michael A. Ruegg, Sasan Cyrusian
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Publication number: 20020176186Abstract: A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Inventors: Sasan Cyrusian, Stephen J. Franck, Sriharsha Annadore, Elmar Bach, Siegfried Hart, Thomas Blon, William G. Bliss, James Wilson Rae, Michael Ruegg, Ulrich Huewels, Fritz Mistlberger
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Publication number: 20020176299Abstract: A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality of clock pulse waves, each having substantially equal period and each being out of phase with respect to other clock pulse waves; an output including at least one output terminal corresponding to one of the clock pulse waves; and a zero phase circuit configured to sequentially couple the plurality of clock pulse waves to the corresponding output terminals.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies N.A., Inc.Inventors: Michael A. Ruegg, Sasan Cyrusian
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Publication number: 20020175740Abstract: A high-speed multiplexer that includes a reduced number of components in the pull-up and/or the pull-down circuits operates faster than conventional multiplexers and can process higher frequency input signals. The pull-up circuit may be a singe p-type MOSFET transistor and the pull-down circuit may be a single n-type MOSFET transistor. The switching circuits may include transistor-based NOR gates. The multiplexer may have numerous channels, for example 2 to 256 or more channels.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies North America Corp.Inventors: Michael Ruegg, Sasan Cyrusian
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Publication number: 20020175772Abstract: A delay stage for inclusion in a semiconductor device is well suited for incorporation in a voltage-controlled oscillator for maximizing the peak-to-peak output voltage and enhancing immunity to noise. The delay stage comprises a first amplifier having a first input terminal and a supply terminal for receiving a minimum rail voltage. A second amplifier has a second input terminal and a supply terminal for receiving the minimum rail voltage. A cascade feedback amplifier is coupled to the first amplifier and the second amplifier. The cascade feedback amplifier has a first output and a second output for providing an output voltage between or approximately equal to at least one of a maximum rail voltage and the minimum rail voltage. A current controller is arranged to vary a resistive load presented to the cascade feedback amplifier. The resistive load is associated with a current flowing to or from the maximum voltage rail.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies North America Corp.Inventors: Sasan Cyrusian, Michael A. Ruegg
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Publication number: 20020176194Abstract: A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant bit counter. The least-significant-bit counter is programmed to an initial state and configured to decrement a state with each pulse of a clock wave. The least-significant-bit counter provides an output signal when the least-significant-bit counter has a zero-count state. The most-significant-bit counter decrements when the least-significant-bit counter has a zero-count state and provides an output signal when the least-significant-bit counter has a zero-count state. A counter output pulse is generated and the high-speed counter is reset to the initial state when both the least-significant bit counter and the most-significant bit counter have a zero-count state.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies N.A., Inc.Inventors: Michael A. Ruegg, Sasan Cyrusian
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Publication number: 20020175724Abstract: An input signal is received having a period and an input pulse width. The input pulse width of an input signal is adjusted to an output pulse width of an output signal based upon a recording control signal for control of recording on a storage medium. The output signal and the output pulse width is derived from a triggering edge of a first selected signal of a first selected phase and a triggering edge of a second selected signal of a second selected phase in succession. The first selected signal and the second selected signal are selected from an assortment of reference signals that have distinct relative phases to provide the output pulse width of a desired duration. The number of distinct relative phases available for formation of the output pulse width is increased by one or more of the following: delaying, dividing, inverting, and interpolating one or more reference signals.Type: ApplicationFiled: May 25, 2001Publication date: November 28, 2002Applicant: Infineon Technologies North America Corp.Inventors: Sasan Cyrusian, Michael A. Ruegg