Abstract: High-voltage finFET semiconductor devices (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an integrated high-voltage switch includes a high-voltage p-type fin field effect transistor (HVP finFET), a high-voltage depletion fin field effect transistor (HVD finFET), and an active area extending across both the HVP finFET and the HVD finFET. The HVP finFET includes a first plurality of fin trenches formed in the active area, a first plurality of fins defined at least in part by the first plurality of fin trenches, and a first gate extending across the first plurality of fins. The HVD finFET includes a second plurality of fin trenches formed in the active area, a second plurality of fins defined at least in part by the second plurality of fin trenches, and a second gate extending across the second plurality of fins.

Abstract: High-voltage semiconductor devices with extended active areas (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a high-voltage semiconductor device includes a high-voltage N-well formed in a substrate. The high-voltage N-well includes a mask edge corresponding to a location of an N-well junction formed in the substrate. The device further includes (i) an active area and (ii) a local deep trench isolation region positioned within the substrate and laterally adjacent to the high-voltage N-well. The active area can extend beyond the mask edge of the high-voltage N-well such that a region of the active area is positioned between the mask edge of the high-voltage N-well and the local deep trench isolation region. The extended active area is expected to improve breakdown voltage characteristics of the device when using local deep trench isolation.

Abstract: Interfaces between higher voltage and lower voltage wafers and related apparatuses and methods are disclosed. An apparatus includes a memory wafer and a logic wafer. Data storage elements of an array are configured to perform an operation responsive to an operational voltage potential. The memory wafer also includes bitlines electrically connected to the data storage elements and isolation devices electrically connected to the bitlines. The logic wafer is bonded to the memory wafer. The logic wafer includes logic circuitry electrically connected to the bitlines through the isolation devices. A maximum voltage potential difference tolerance of the logic circuitry is less than an operational voltage potential difference between the operational voltage potential and a reference voltage potential of the logic circuitry.

Abstract: Disclosed herein are methods, apparatuses and systems including breakdown voltage management mechanisms. In some embodiments, a semiconductor circuit includes one or more moat trenches disposed between a circuit component and a deep trench that separates adjacent circuit components.

Abstract: Memory circuitry comprises strings of NAND memory cells and horizontal high voltage transistors that are operatively electrically coupled with the vertical strings. The horizontal high voltage transistors individually comprise two horizontally-spaced regions having a vertical fin extending horizontally there-between. Two source/drain regions are individually in one of the two horizontally-spaced regions and individually comprise a highest-doped region that is horizontally spaced from the vertical fin and a lightly-doped region that is beneath and laterally aside the highest-doped region between the highest-doped region and the vertical fin (with the lightly-doped region being horizontally spaced from the vertical fin by an intermediate region of one of the two horizontally-spaced regions). A channel region is horizontally between the two source/drain regions and is in the vertical fin and in each intermediate region.

Abstract: A semiconductor device is described in this disclosure. The semiconductor device includes a first semiconductor channel, a second semiconductor channel parallel to the first semiconductor channel, and a gate disposed above the first semiconductor channel and the second semiconductor channel. In addition, the semiconductor device includes a string driver and dummy devices coupled to the string driver, wherein dummy devices are biased at Vpass to better emulate transistor bias behavior of the string driver by capturing the Vt/Dvt modulating effect of the Vpass on the neighbor devices. Further, the semiconductor device is coupled with a program voltage regulator circuit to emulate neighbor bias effort on the string driver.

Abstract: A string driver device is described in this disclosure. The string driver device includes a semiconductor channel disposed in an upper portion of a semiconductor substrate and a gate dielectric layer disposed above the semiconductor channel. The string driver device also includes a source region and a drain region disposed at opposite sides of the semiconductor channel, each of the source region and the drain region having a corresponding contact disposed thereon. The string driver device further includes a gate that is disposed above the gate dielectric layer and has a first length, and a field plate layer disposed above the gate, the field plate layer having a second length larger than the first length of the gate, wherein the field plate layer includes one or more edge regions extending across the semiconductor channel edge and toward the source region or the drain region.

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

Abstract: Disclosed is a method which may include providing a battery cell sensing application specific integrated circuit comprising at least a first channel and a second channel, a first connection line connected to the first channel and a second connection line connected to the second channel, a first weld pad connected to the first connection line, a second weld pad connected to the second connection line, and binding a first shunt to the first weld pad and the second weld pad.

Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor can include a gate disposed between a source area and a drain area of the transistor. The transistor can also include a plurality of routing lanes above the gate for use by automated routing programs that layout metal connections for the apparatus. A first field plate can be disposed above a LDD region of the source area with the first field plate being on a same level as the plurality of routing lanes. A second field plate can be disposed above a LDD region of the drain area with the second field plate being on the same level as the plurality of routing lanes. The first and second field plates can be electrically connected to the gate using respective first and second path that bypass the plurality of routing lanes.

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

Abstract: Integrated circuit structures might include a semiconductor material, a first active area in the semiconductor material, a second active area in the semiconductor material, and an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area. The isolation structure might further include a first edge portion extending below a surface of the semiconductor material to a first depth, a second edge portion extending below the surface of the semiconductor material to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth.

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor can include a gate disposed between a source area and a drain area of the transistor. The transistor can also include a plurality of routing lanes above the gate for use by automated routing programs that layout metal connections for the apparatus. A first field plate can be disposed above a LDD region of the source area with the first field plate being on a same level as the plurality of routing lanes. A second field plate can be disposed above a LDD region of the drain area with the second field plate being on the same level as the plurality of routing lanes. The first and second field plates can be electrically connected to the gate using respective first and second path that bypass the plurality of routing lanes.

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

Abstract: A sealing element for sealing a gap between a first member and a second member includes an annular seal body having an inner surface, an outer surface and a pair of side surfaces each connected between opposite ends of the inner surface and the outer surface. A first square garter spring embedded within at least one of an inner and an outer corner of the annular seal body.

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.