Patents by Inventor Michael A. Smith

Michael A. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278286
    Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: April 15, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 12274057
    Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 12237278
    Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Kenneth W. Marr
  • Publication number: 20240428859
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Inventors: Michael A. Smith, Martin W. Popp
  • Publication number: 20240390693
    Abstract: To distribute electrical treatment to a treatment area of a patient, described herein are electrical apparatuses, methods of their operation and methods for delivery of the electrical treatment to the patient. In some embodiments, the treatment applicator comprises an electrode assembly that includes at least two electrodes, and a conductive spacer positioned between the electrodes. Methods of treatment and methods of operation of the apparatuses and systems of the present disclosure are also provided.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 28, 2024
    Inventors: Cameron D. HINMAN, Michael A. SMITH, Kenneth R. KRIEG
  • Patent number: 12112804
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Martin W. Popp
  • Publication number: 20240322049
    Abstract: A semiconductor device including a first semiconductor device that includes a substrate, a memory array disposed above the substrate and below a frontside surface of the first semiconductor device, a plurality of source region contact (SRC) nodes disposed under the memory array, and a plurality of high-voltage (HV) diodes disposed in the substrate, each of the plurality of HV diodes being connected to corresponding one of the plurality of SRC nodes; and a second semiconductor device including a plurality of complementary-metal-oxide semiconductor (CMOS) devices, each of the plurality of CMOS devices being connected to, through a backside surface of the second semiconductor device and the frontside surface of the first semiconductor device, corresponding bond pad of the memory array, wherein fusion bonding exists between the backside surface of the second semiconductor device and the frontside surface of the first semiconductor device.
    Type: Application
    Filed: February 27, 2024
    Publication date: September 26, 2024
    Inventors: Shyam Surthi, Haitao Liu, Michael A. Smith
  • Publication number: 20240290787
    Abstract: A string driver device including a substrate; and a plurality of string driver array blocks that are disposed above the substrate, each of the plurality of string driver array blocks including a plurality of active regions that are parallelly aligned along a length direction, a plurality of shared gates that are disposed above the plurality of active regions and along a width direction, the width direction being perpendicular to the length direction, a through silicon isolation (TSI) region that surrounds the plurality of active regions on the substrate and that is disposed between neighboring active regions of the plurality of active regions, and a plurality of shallow trench isolation (STI) regions that are disposed adjacent to one or more channel regions of each of the plurality of active regions and below the plurality of shared gates respectively.
    Type: Application
    Filed: January 27, 2024
    Publication date: August 29, 2024
    Inventor: Michael A. Smith
  • Publication number: 20240274594
    Abstract: A semiconductor device including a substrate; a plurality of active regions that are disposed on the substrate and that are parallelly aligned; a plurality of first type of trench isolations having a first top critical dimension (CD), each of the plurality of the first type of trench isolations including sidewalls that taper towards one another along a depth direction; and a plurality of second type of trench isolations having a second top CD, the second top CD being larger than the first top CD and each of the plurality of the second type of trench isolations having a flat bottom trench surface.
    Type: Application
    Filed: January 29, 2024
    Publication date: August 15, 2024
    Inventors: Shyam Surthi, Michael A. Smith
  • Publication number: 20240274533
    Abstract: A semiconductor device assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver, wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.
    Type: Application
    Filed: January 18, 2024
    Publication date: August 15, 2024
    Inventors: Michael A. Smith, Martin W. Popp, Richard J. Hill
  • Publication number: 20240234311
    Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.
    Type: Application
    Filed: March 20, 2024
    Publication date: July 11, 2024
    Inventors: Michael A. Smith, Haitao Liu, Vladimir Mikhalev
  • Patent number: 12015026
    Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Kenneth W. Marr
  • Publication number: 20240154033
    Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 9, 2024
    Inventor: Michael A. Smith
  • Patent number: 11973031
    Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Haitao Liu, Vladimir Mikhalev
  • Publication number: 20240107754
    Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Michael A. Smith
  • Publication number: 20240072057
    Abstract: Semiconductor devices including an adjusted bottom/deep well embedded in a semiconductor substrate. The adjusted bottom/deep well having one or more characteristics resulting from being formed using or through a temporary masked layer.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventor: Michael A. Smith
  • Patent number: 11901448
    Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Publication number: 20240038904
    Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 1, 2024
    Inventor: Michael A. Smith
  • Patent number: 11889687
    Abstract: Integrated circuit structures might include a semiconductor material, a first active area in the semiconductor material, a second active area in the semiconductor material, and an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area. The isolation structure might further include a first edge portion extending below a surface of the semiconductor material to a first depth, a second edge portion extending below the surface of the semiconductor material to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 11881528
    Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor includes a source and a source contact disposed on the source. The transistor also includes a drain and a drain contact disposed on the drain. A gate is disposed between the source contact and the drain contact, and a screened region is disposed adjacent the source contact or the drain contact. The screened region corresponds to a lightly doped region. The screened region includes an implant screen configured to reduce an effective dose in the screened region so as to shift an acceptable dose range of the screened region to a higher dose range. The acceptable dose range corresponds to acceptable breakdown voltage values for the screened region.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith