Abstract: An iron-air battery including an iron electrode in contact with an anode current collector, wherein the iron electrode includes a plurality of channels; an oxygen reduction reaction electrode having a first surface facing the plurality of channels and an opposing second surface in contact with air; an oxygen evolution reaction electrode interdigitated with the plurality of channels of the iron electrode, wherein at least a portion of the oxygen evolution reaction electrode is disposed within the plurality of channels in a direction perpendicular to a plane of the oxygen reduction reaction electrode; and an electrolyte in contact with the iron electrode, the first surface of the oxygen reduction reaction electrode, the plurality of channels, and the oxygen evolution reaction electrode.

Abstract: A light bulb with at least one USB port is provided. The light bulb includes a translucent housing having an open bottom. A light emitter is disposed within the translucent housing so as to emit light through the housing. A base is secured to the open bottom of the translucent housing. The base includes an electrical connector connected to the light emitter and operable to connect with a light socket. For example, the electrical connector may be a male threaded electrical connector. At least one USB port, such as a pair of USB ports, is disposed in the base and connected to the electrical connector.

Abstract: A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.

Abstract: A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

Abstract: A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.

Abstract: A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

Abstract: A programmable LED display system is disclosed. The system includes a programmable controller; a driver operative to generate a control signal in response to a signal provided by the programmable controller; and a display device operative to provide a visual representation of the state of the system in response to the control signal. The system also includes means for determining which state condition is displayed when more than one state condition exists.

Abstract: A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A programmable LED display system is disclosed. The system includes a programmable controller, a driver operative to generate a control signal in response to a signal provided by the programmable controller, and a display device operative to provide a visual representation of the state of the system in response to the control signal. The system also includes means for determining which state condition is displayed when more than one state condition exists.

Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A programmable LED display system is disclosed. The system includes a programmable controller; a driver operative to generate a control signal in response to a signal provided by the programmable controller; and a display device operative to provide a visual representation of the state of the system in response to the control signal. The system also includes means for determining which state condition is displayed when more than one state condition exists.

Abstract: A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

Abstract: A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

Abstract: A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended transceivers connected to the communications network device. Confidential or user sensitive information is not conveyed to the unintended transceivers since the invalid symbol is defined independent of the data. The invalid symbol unambiguously informs the unintended transceivers that the data in the data packet is invalid.

Abstract: A PHY having a media independent interface (MII) providing connections to a MAC or to another PHY is disclosed. The invention provides a mechanism for connecting a first PHY with a second PHY, wherein the PHY may act as the media access control side of the MII. The system includes a selection means for selecting the mode of operation for the PHY, a MII for providing a synchronous digital interface carrying un-encoded data over separate transmit and receive paths and a translation entity for generating output enables for controlling the flow of the data, wherein the translation entity establishes in response to mode being selected a first flow of data for connecting the PHY to a Media Access Control entity or a second flow of data for connecting the PHY to a second PHY. The translation entity muxes data and control signals based upon the mode selection. A translation synchronization entity is provided.

Abstract: A system for integrating multiple repeaters into a single collision domain employs both analog and digital circuitry to convey system-wide collision information to repeaters thereby allowing seamless integration of multiple repeaters into multiple hubs without requiring additional drivers or external glue logic. One signal line (CFSL) within each hub is used to aggregate collision information within the hub. Further, only one signal line (CFSS) is used to aggregate collision information between hubs. This latter signal line in conjunction with two intra-hub signal lines (COLZ and SNGLZ) distributes system-wide collision information to all of the repeaters in all of the hubs.

Abstract: A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended transceivers connected to the communications network device. Confidential or user sensitive information is not conveyed to the unintended transceivers since the invalid symbol is defined independent of the data. The invalid symbol unambiguously informs the unintended transceivers that the data in the data packet is invalid.