Abstract: A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.

Abstract: A graphics system including a frame buffer and a processing unit. The frame buffer contains N slots per pixel. Slots are used to store fragments. Suppose the N slots for a given pixel are occupied. In response to having received (or generated) a new fragment for the pixel, the processing unit may (a) blend the two backmost slots to liberate space for the new fragment, (b) blend the new fragment with the backmost slot in a first order, or, (c) blend the new fragment and the backmost slot in a second order. The choice of (a), (b) or (c) depends on the relationship of the new fragment's z value to the z values of the two backmost slots. The processing unit may be programmably configured to perform multi-pass order independent transparency in either front-to-back order or back-to-front order.

Abstract: A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the screen, a new design utilizes chips working in series. Each chip is responsible for a different interleaved region of screen space. Each chip performs part of the convolution process for a pixel and sends a partial result on to the next chip. The final chip completes the convolution and stores the filtered pixel. An alternate design interconnects chips in groups. The chips within a group operate in series, whereas the groups may operate in parallel.

Abstract: A graphics system invokes a dicing process if one or more edges of a triangle T have length greater than a maximum length (LMAX), invokes a central subdivision process if a coverage estimate for the triangle T is greater than a maximum coverage and all edges of triangle T have length less than or equal to LMAX, invokes rendering of a sequence of one or more single-layer triangles based on triangle T if the coverage estimate for triangle T is less than or equal to the maximum coverage and all edges have length less than or equal to LMAX. Said invocation of rendering of the sequence of single-layer triangles results in the application of a plurality of texture layers to samples corresponding to triangle T. The samples are stored in the TAB between the application of successive layers of said plurality of texture layers.

Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.

Abstract: A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.

Abstract: A system and method are disclosed for a rasterization pipeline with a parallel initialization path that may provide an increased rate of triangle processing. The edge walker, span walker, and sample generator modules of a rasterization pipeline may be modified to enable the next primitive in the sequence of primitives to be initialized, while the current primitive is processed. Consequently, these two processes that were done in series may now be done in parallel. Data transmitted between modules may be separated into initialization data (data the module needs to define a primitive) and primitive data (the processed output of each module). The second path is for additional initialization data, which allows each of these modules to receive the initialization data for the next primitive, while processing the primitive data for the current primitive.

Abstract: A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.

Abstract: A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.

Abstract: A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: A signature capture and analysis system suitable for use in a high performance computer graphics system is described. The system employs a distributed network of signature analysis registers (SARs) which may be configured to capture and accumulate information from one or more channels of data over pre-defined periods of time. The SARs may be so distributed to allow for the isolation of faults to a sub-system level. The signature values developed in these SARs are, in some cases pre-seeded, and may include contributions from both data and control signals. Checking of the signature values against known good or expected outcomes is provided for. In some cases the SARs may be implemented as linear hybrid cellular automatons.

Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.

Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.

Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.

Abstract: A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.

Abstract: A graphics system may be configured to render anti-aliased dots in terms of samples and to generate pixels by filtering the samples. The pixels are supplied to one or more display devices. The means used to generate the samples may perform the computation of radial distance at positions on a grid in a rendering coordinate space, and interpolate estimates for the radial distances of samples around the dot as needed based on the radii at the grid positions.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.