Abstract: A capacitive system includes a module circuit card assembly including a first modular keying and alignment mechanism and a second modular keying and alignment mechanism. The first and second modular keying and alignment mechanisms are configured for mechanical alignment and electrical connection with a backplane circuit card assembly (CCA). A capacitor is mounted to the module circuit card assembly and is electrically connected to each of the first and second modular keying and alignment mechanisms through a charge/discharge circuit. The circuit is configured to: charge the capacitor with the module circuit card assembly connected to the backplane CCA, discharge the capacitor with the module circuit card assembly connected to the backplane CCA for providing backup power, and discharge the capacitor through a bleed resistor of the circuit upon disconnection of the module circuit card assembly from the backplane CCA.

Abstract: Provided are embodiments for monitoring clock drift. Embodiments may include an XOR gate that is configured to receive a first clock signal from a first clock source and a second clock signal from a second clock source, wherein the XOR logic gate is further configured to generate a switching output based on an XOR operation of the first clock signal and the second clock signal, and a rising edge detector and a falling edge detector that are configured to detect a rising edge and a falling edge of the switching output. Embodiments may also include an AND gate that is configured to threshold compare the rising edge to a configurable threshold to determine if a fault condition exists indicating clock drift between the first clock signal and the second clock signal and provide an indication of the fault condition based at least in part on the comparison.

Abstract: Provided are embodiments for monitoring clock drift. Embodiments may include an XOR gate that is configured to receive a first clock signal from a first clock source and a second clock signal from a second clock source, wherein the XOR logic gate is further configured to generate a switching output based on an XOR operation of the first clock signal and the second clock signal, and a rising edge detector and a falling edge detector that are configured to detect a rising edge and a falling edge of the switching output. Embodiments may also include an AND gate that is configured to threshold compare the rising edge to a configurable threshold to determine if a fault condition exists indicating clock drift between the first clock signal and the second clock signal and provide an indication of the fault condition based at least in part on the comparison.

Abstract: Systems, methods, and computer program products for sinusoidal nulling are provided. Aspects include transmitting, by a controller, an excitation signal to a first sensor, determining, by the controller, a target harmonic based at least on one or more characteristics of the excitation signal, receiving a return signal from the first sensor, sampling the return signal at a first sample rate based on the target harmonic, and adjusting a phase of the sampled return signal to null the target harmonic amplitude to form an adjusted return signal.

Abstract: A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period.

Abstract: A system comprises a first current balancer and a second current balancer. Each of the first and second current balancers includes a first input line for a first voltage source connected to a first output, a second input line for a second voltage source connected to a second output and is in parallel with the first input line, a first series pass element connected in series with the first input line, and a second series pass element connected in series with the second input line. The system further includes a controller operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A system includes a first input line for a first voltage source, wherein the first input line is connected to a first output. A second input line is included for a second voltage source, wherein the second input line is connected to a second output and is in parallel with the first input line. A first series pass element is connected in series with the first input line, and a second series pass element is connected in series with the second input line. A controller is operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A system comprises a first current balancer and a second current balancer. Each of the first and second current balancers includes a first input line for a first voltage source connected to a first output, a second input line for a second voltage source connected to a second output and is in parallel with the first input line, a first series pass element connected in series with the first input line, and a second series pass element connected in series with the second input line. The system further includes a controller operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A system includes a first input line for a first voltage source, wherein the first input line is connected to a first output. A second input line is included for a second voltage source, wherein the second input line is connected to a second output and is in parallel with the first input line. A first series pass element is connected in series with the first input line, and a second series pass element is connected in series with the second input line. A controller is operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: An improved low-profile antenna has a radiating element disposed apart from a ground plane, with at least one microstrip disposed between the radiating element and the ground plane. A feed is electrically coupled to the radiating element and to the at least one microstrip. The at least one microstrip is also electrically coupled to the ground plane, completing a closed path. When driven by an electrical signal, the antenna more efficiently generates electromagnetic signals in the horizontal direction and also has decreased sensitivity to foreign objects.

Abstract: A system for determining an amplitude of a sinusoidal output waveform from a sensor includes a controller configured to provide a sample signal having a sample frequency that is four times a frequency of a sinusoidal excitation waveform provided to the sensor. The sensor has inductively-coupled primary and secondary windings that produce the sinusoidal output waveform from the secondary winding when the excitation waveform is provided to the primary winding. An analog-to-digital converter measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and the system calculates the amplitude based on the measurements of the first and second voltages.

Abstract: Systems, methods, and computer program products for sinusoidal nulling are provided. Aspects include transmitting, by a controller, an excitation signal to a first sensor, determining, by the controller, a target harmonic based at least on one or more characteristics of the excitation signal, receiving a return signal from the first sensor, sampling the return signal at a first sample rate based on the target harmonic, and adjusting a phase of the sampled return signal to null the target harmonic amplitude to form an adjusted return signal.

Abstract: A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period.

Abstract: A system for determining a phase angle of a sensor waveform relative to an excitation waveform includes a controller that provides an excitation signal having an excitation frequency and a sample signal having four times the excitation frequency. An exciter provides a sinusoidal excitation waveform at the excitation frequency to a primary winding, thereby inducing a sensor waveform in a secondary winding. An analog-to-digital converter (ADC) measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and a wrap-around ADC measures a first and second voltage of the sinusoidal excitation waveform. The first voltage measurements are made at the same time, and the second voltage measurements are made at the same time. The system calculates the phase angle based on the first voltage measurements and the second voltage measurements.

Abstract: A system for determining a phase angle of a sensor waveform relative to an excitation waveform includes a controller that provides an excitation signal having an excitation frequency and a sample signal having four times the excitation frequency. An exciter provides a sinusoidal excitation waveform at the excitation frequency to a primary winding, thereby inducing a sensor waveform in a secondary winding. An analog-to-digital converter (ADC) measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and a wrap-around ADC measures a first and second voltage of the sinusoidal excitation waveform. The first voltage measurements are made at the same time, and the second voltage measurements are made at the same time. The system calculates the phase angle based on the first voltage measurements and the second voltage measurements.

Abstract: A system for determining an amplitude of a sinusoidal output waveform from a sensor includes a controller configured to provide a sample signal having a sample frequency that is four times a frequency of a sinusoidal excitation waveform provided to the sensor. The sensor has inductively-coupled primary and secondary windings that produce the sinusoidal output waveform from the secondary winding when the excitation waveform is provided to the primary winding. An analog-to-digital converter measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and the system calculates the amplitude based on the measurements of the first and second voltages.

Abstract: A solenoid electrical diagnostic system includes a solenoid circuit operable in response to an electrical current. A low-side switch includes a low-side input configured to receive a pulsed voltage signal and a low-side output in signal communication with the solenoid circuit. The low-side switch continuously switches between an on-state and an off-state based on the pulsed voltage signal to adjust a level of the current flowing through the solenoid circuit. A solenoid monitoring unit generates a low-side output state signal based on an output voltage at the low-side output, and a low-side input state signal based on an input voltage at the low-side input. The solenoid electrical diagnostic system further includes an electronic hardware controller determines at least one operating condition of the solenoid circuit based on a comparison between the state signals and a threshold value.

Abstract: A fast shut-off solenoid circuit network includes a solenoid circuit and a current dissipation circuit. The solenoid circuit is operable in response to an electrical current, and configured to operate in an enable mode and a disable mode. The current dissipation circuit is configured to dissipate the current discharged from the solenoid circuit in response to invoking the disable mode. The fast shut-off solenoid circuit network further includes a dissipation bypass circuit. The dissipation bypass circuit is configured to divert the current discharged by the solenoid circuit away from current dissipation circuit when operating in the enable mode.

Abstract: An improved low-profile antenna has a radiating element disposed apart from a ground plane, with at least one microstrip disposed between the radiating element and the ground plane. A feed is electrically coupled to the radiating element and to the at least one microstrip. The at least one microstrip is also electrically coupled to the ground plane, completing a closed path. When driven by an electrical signal, the antenna more efficiently generates electromagnetic signals in the horizontal direction and also has decreased sensitivity to foreign objects.

Abstract: A voltage monitor system includes a voltage rail. A voltage monitor is operatively connected to the voltage rail to monitor voltage of the voltage rail with at least one input connection. A self-test module is operatively connected to the voltage rail to perturb voltage at the at least one input connection of the voltage monitor for testing the voltage monitor.