Abstract: In a multinode switch array, the maximum number of nodes that can be passing data from input to output lead can be no greater than the number of output leads in the array. Thus, the remaining nodes, while not performing a useful switch function, when implemented in CMOS (complementary metal oxide semiconductor), are consuming power due to changing logic levels in the circuitry and are causing the input data drivers to consume power due to the loading effect of the non-functional but actively connected nodes. The present invention overcomes these prior art disadvantages by ascertaining from the indirect address data stored in connect memory of each node, the times that the traffic memory needs to be activated and deactivates the memory and any associated driver at all other times in a manner such that it and the data driver are not consuming power incurred by data transfer operations.

Abstract: The present invention relates to a checking circuit concept which determines the integrity of data passing through a further circuit to be checked such as an elastic buffer. The concept is based on the fact that a serial data stream entering an elastic buffer must exit the elastic buffer intact without bit errors. Since the bit delay through the elastic buffer is a variable, it becomes difficult to test bit integrity. The present invention determines the bit integrity by sampling and storing a sequential set of data entering the elastic buffer and successively comparing it to data exiting the buffer. If no errors are present, the stored input data will match the data exiting the elastic buffer within N bits where N equals the storage bit location size of the elastic buffer.