Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Abstract: A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.

Abstract: A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Abstract: Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.

Abstract: Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.

Abstract: Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.

Abstract: Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.

Abstract: Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.

Abstract: Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.

Abstract: Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.

Abstract: Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.

Abstract: Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.

Abstract: An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.

Abstract: Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal.

Abstract: In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.

Abstract: In a method for reducing and/or eliminating mismatch in one or more devices that require a balanced state (e.g., in cross-coupled transistors in each memory cell and/or sense amp in a memory array), the bias (i.e., the preferred state) of each of the devices is determined. Then, a burn-in process is initiated, during which an individually selected state is applied to each of the devices. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.