Abstract: A self-tapping screw (10, 30) comprising a drive (12) and a shank (14) bearing a thread comprising a main thread (16, 32), wherein the main thread (16, 32) has a maximum main thread external diameter (DAF) and a cutting area (F) and a supporting area (T) following in the direction of the drive (12), wherein the shank (14) has a threaded end (18) at an end opposite the drive (12), with the screw end (18) having a diameter (DE) of at least 20% of the maximum main thread external diameter (DAF), The shank further has, in the region of the screw end (18), a tap flute (20), wherein the tap flute (20) comprises at least two tapping thread turns (20a, 20b, 20c) which attain, in their external diameter (DAA), no more than 90% of the maximum main thread external diameter (DAF) and form a tap region in which the tapping thread turns (20a, 20b, 20c) have the same diameter development, and in addition in that the diameter of the main thread (16, 32) in the tap flute region (AB) is less than or equal to the diameter (DAA)

Abstract: The invention relates to a method for producing a screw, having the following steps: (a) rolling a screw wire made of low-alloy carbon steel to produce screw (10) having a thread; (b) heating the entire screw (10) to an austenitizing temperature under a carbon atmosphere and/or nitrogen atmosphere and maintaining the temperature; (c) quenching the entire screw (10) to a bainitizing temperature and maintaining the bainitizing temperature until the screw has a bainitic structure over its cross-section. The invention is characterized in that the screw (10) is subsequently hardened locally at its tip (22), by the tip (22) being heated to an austenitizing temperature and the screw (10) being subsequently quenched to a temperature below the martensite starting temperature (MS).

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Abstract: The invention relates to a screw (IO) in order to cut a mating thread in a plastic article, comprising a lower threaded part (F) and an upper threaded part (T), the lower threaded part having a larger diameter and its tip covering a larger surface than the upper threaded part.

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Abstract: A self-tapping screw (10, 30) comprising a drive (12) and a shank (14) bearing a thread comprising a main thread (16, 32), wherein the main thread (16, 32) has a maximum main thread external diameter (DAF) and a cutting area (F) and a supporting area (T) following in the direction of the drive (12), wherein the shank (14) has a threaded end (18) at an end opposite the drive (12), with the screw end (18) having a diameter (DE) of at least 20% of the maximum main thread external diameter (DAF), The shank further has, in the region of the screw end (18), a tap flute (20), wherein the tap flute (20) comprises at least two tapping thread turns (20a, 20b, 20c) which attain, in their external diameter (DAA), no more than 90% of the maximum main thread external diameter (DAF) and form a tap region in which the tapping thread turns (20a, 20b, 20c) have the same diameter development, and in addition in that the diameter of the main thread (16, 32) in the tap flute region (AB) is less than or equal to the diameter (DAA)

Abstract: The invention relates to a connecting element (10, 30) for connecting at least two components that are positioned one on top of the other, comprising a shaft (14, 34) and a head (12, 32), which is provided with a drive (38), the shaft (14, 34) being formed from a base material and ending at the exposed shaft end thereof that is opposite the head (12, 32). The invention is characterised in that a tip (16, 40) made of plating material is applied to the exposed shaft end, which plating material is different from the base material.

Abstract: The invention relates to a thread-forming screw (10) comprising a base body (12, 20) which comprises a drive and a screw shank, the screw shank carrying a thread (13) having a channeling region (14) and a carrying region, the base body (12, 20) consisting of a base material. The invention is characterized in that the thread (13) is formed from a coating material (18) different from the base material, at least in the channeling region (14), which is applied to the base material by deposition welding.

Abstract: The invention relates to a thread-forming screw (10) comprising a base body (12, 20) which comprises a drive and a screw shank, the screw shank carrying a thread (13) having a channeling region (14) and a carrying region, the base body (12, 20) consisting of a base material. The invention is characterized in that the thread (13) is formed from a coating material (18) different from the base material, at least in the channeling region (14), which is applied to the base material by deposition welding.

Abstract: A resealable package, the resealable package comprising a polymeric substrate, the polymeric substrate comprising a first side panel, a second side panel, a closed bottom and an opening, the opening comprising a first side region and a second side region and the first side region and the second side region comprise a magnetizable composition, the magnetizable composition comprises a thermoplastic polymer and magnetizable particles and the magnetizable composition is aligned and magnetized to form a first magnet along the first side region and a second magnet along the second side region. The first magnet comprises a plurality of poles having a first leading edge comprising a first pole and the second magnet comprises a plurality of poles having a second leading edge comprising a second pole that is opposite to the first pole.

Abstract: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also include marking at least one second entry in the queue is ready to be picked for execution in response to at least one second tag associated with at least one second entry in the queue matching the first tag.

Abstract: A method includes suppressing execution of at least one dependent instruction of a load instruction by a processor using stored dependency information responsive to an invalid status of the load instruction. A processor includes an execution unit to execute instructions and a scheduler. The scheduler is to select for execution in the execution unit a load instruction having at least one dependent instruction and suppress execution of the at least one dependent instruction using stored dependency information responsive to an invalid status of the load instruction.

Abstract: A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a scheduler, and a controller. The scheduler selects for execution in the execution unit a load instruction having at least one dependent instruction. The controller, responsive to the scheduler selecting the load instruction, selectively awakens the at least one dependent instruction based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution by the execution unit.

Abstract: A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.

Abstract: A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. The scheduler unit includes a scheduler queue and is operable to store a load-operation in the scheduler queue. The load-operation instruction includes a load portion and an operation portion. The scheduler unit schedules the load portion for execution in the execution unit, marks the operation portion in the scheduler queue as eligible for execution responsive to scheduling the load portion, receives an indication of an invalid status of the load portion, and suppresses execution of the operation portion responsive to the indication of the invalid status.

Abstract: A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping of physical registers to the set of architectural registers using the stored information.

Abstract: A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.

Abstract: A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping of physical registers to the set of architectural registers using the stored information.