Patents by Inventor Michael Alexander Bowen
Michael Alexander Bowen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104282Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Benjamin Neil Trombley, Chung-Lung K. Shum, Paul G. Villarrubia, K. Paul Muller, Michael Hemsley Wood, Daniel Arthur Gay, Hua Xiang, Karl Evan Smock Anderson, Erica Stuecheli, Michael Alexander Bowen, Randall J. Darden
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Patent number: 11941340Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.Type: GrantFiled: August 16, 2021Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: Michael Alexander Bowen, Gerald L Strevig, III, Amanda Christine Venton, Robert Mahlon Averill, III, Adam P. Matheny, David Wolpert, Mitchell R. DeHond
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Patent number: 11922109Abstract: Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.Type: GrantFiled: August 12, 2021Date of Patent: March 5, 2024Assignee: International Business Machines CorporationInventors: Amanda Christine Venton, Michael Alexander Bowen, Rahul M. Rao
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Publication number: 20230051392Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.Type: ApplicationFiled: August 16, 2021Publication date: February 16, 2023Inventors: Michael Alexander Bowen, Gerald L Strevig, III, Amanda Christine Venton, Robert Mahlon Averill, III, Adam P. Matheny, David Wolpert, Mitchell R. DeHond
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Publication number: 20230048876Abstract: Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Amanda Christine Venton, Michael Alexander Bowen, Rahul M. Rao
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Patent number: 11341311Abstract: Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.Type: GrantFiled: June 24, 2021Date of Patent: May 24, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Koone, Smitha Reddy, Gustavo Enrique Tellez, Michael Alexander Bowen, Adam P. Matheny
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Patent number: 7921399Abstract: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to its original net list state while keeping the routing solution.Type: GrantFiled: February 18, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Michael Alexander Bowen
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Publication number: 20090210850Abstract: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to it's original net list state while keeping the routing solution.Type: ApplicationFiled: February 18, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Michael Alexander Bowen
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Patent number: 6338025Abstract: An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.Type: GrantFiled: October 8, 1998Date of Patent: January 8, 2002Assignee: International Business Machines Corp.Inventors: Michael Alexander Bowen, Byron Lee Krauter, Steven Arthur Schmidt, Clay Chip Smith, Amy May Tuvell
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Patent number: 6279142Abstract: A method of on-chip interconnect design in an integrated circuit (IC) is provided. Fast circuit simulations of each net constituting the IC are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasitic cross-coupling capacitances and shunt capacitances derived from three-dimensional field solver evaluations of pre-routing phase estimated wire geometries. If the noise margin and slew rate criteria are not satisfied for the net under simulation, the simulations are iterated, with a new wire geometry selected between iterations, until the criteria are satisfied. Each net is tagged with a wire geometry that satisfies noise margin and slew rate requirements which can then be passed to a routing tool.Type: GrantFiled: October 2, 1998Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Michael Alexander Bowen, Moises Cases, Howard Harold Smith
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Patent number: 6028989Abstract: A program method for noise calculation and modeling caculates crosstalk voltage for a planned chip design, by first running routing and crosstalk routines for creating crosstalk rules for the planned design of a chip and loading crosstalk rules after routing is completed, and calculating the noise voltage of the planned design based on the exact topologies/paths of the victim and perpetrator nets of the planned design by path tracing and outputing a program file which contains the calculated noise voltage and a complete tabulation of the key physical and electrical parameters of the victim and perpetrator nets of the planned design, and then modeling using a network analysis program to selected nets of the design which exceed allowed noise limitations and obtaining the planned design net's network topology as an output while using the program file containing noise voltage calculation results as an input to the net's topology circuit simulation modeling program and outputting a nodal voltages vs.Type: GrantFiled: April 13, 1998Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventors: Allan Harvey Dansky, Howard Harold Smith, Fadi Yusuf Busaba, Michael Alexander Bowen, Adrian Zuckerman