Patents by Inventor Michael Alexander KENNEDY
Michael Alexander KENNEDY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004611Abstract: Processing circuitry performs a processing operation to generate a two's complement result value representing a positive or negative number in two's complement representation. Normalization-and-rounding circuitry converts the two's complement result value to a normalized-and-rounded floating-point result value represented using sign-magnitude representation. The normalization-and-rounding circuitry comprises incrementing circuitry to perform an increment addition (e.g. a rounding increment or a conversion increment) to generate a fraction of the normalized-and-rounded floating-point result value. For an operation where the increment addition is required to be performed, tininess detection circuitry detects the after-rounding tininess status based on a still-to-be-incremented version of the normalized-and-rounded floating-point result value prior to the increment addition by the increment circuitry.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Inventors: Michael Alexander KENNEDY, Marco MONTAGNA, Karel Hubertus Gerardus WALTERS, Ian Michael CAULFIELD
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Patent number: 11789701Abstract: A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.Type: GrantFiled: August 5, 2020Date of Patent: October 17, 2023Assignee: Arm LimitedInventors: Tai Li, Jack William Derek Andrew, Michael Alexander Kennedy
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Patent number: 11429426Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.Type: GrantFiled: May 1, 2019Date of Patent: August 30, 2022Assignee: Arm LimitedInventors: Timothy Nicholas Hay, Martin Weidmann, Michael Alexander Kennedy, Andrew John Turner
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Publication number: 20220043631Abstract: A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.Type: ApplicationFiled: August 5, 2020Publication date: February 10, 2022Inventors: Tai LI, Jack William Derek ANDREW, Michael Alexander KENNEDY
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Publication number: 20210271512Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.Type: ApplicationFiled: May 1, 2019Publication date: September 2, 2021Inventors: Timothy Nicholas HAY, Martin WEIDMANN, Michael Alexander KENNEDY, Andrew John TURNER
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Patent number: 11068238Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.Type: GrantFiled: May 21, 2019Date of Patent: July 20, 2021Assignee: Arm LimitedInventors: Michael Alexander Kennedy, Neil Burgess, Zichao Xie, Chiloda Ashan Senarath Pathirane
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Patent number: 10963253Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.Type: GrantFiled: July 10, 2018Date of Patent: March 30, 2021Assignee: Arm LimitedInventors: Karel Hubertus Gerardus Walters, Chiloda Ashan Senarath Pathirane, Michael Alexander Kennedy
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Publication number: 20200371749Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Michael Alexander KENNEDY, Neil BURGESS, Zichao XIE, Chiloda Ashan Senarath PATHIRANE
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Patent number: 10846056Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P?3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.Type: GrantFiled: August 20, 2018Date of Patent: November 24, 2020Assignee: Arm LimitedInventors: Michael Alexander Kennedy, Neil Burgess, Zichao Xie, Karel Hubertus Gerardus Walters
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Publication number: 20200057609Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P?3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Inventors: Michael Alexander KENNEDY, Neil BURGESS, Zichao XIE, Karel Hubertus Gerardus WALTERS
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Publication number: 20200019402Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: Karel Hubertus Gerardus WALTERS, Chiloda Ashan Senarath PATHIRANE, Michael Alexander KENNEDY
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Patent number: 10409604Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X?J and F<Y?K.Type: GrantFiled: January 2, 2018Date of Patent: September 10, 2019Assignee: ARM LimitedInventors: Michael Alexander Kennedy, Neil Burgess
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Publication number: 20180307489Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X?J and F<Y?K.Type: ApplicationFiled: January 2, 2018Publication date: October 25, 2018Inventors: Michael Alexander KENNEDY, Neil BURGESS
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Patent number: 10019394Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: GrantFiled: March 21, 2017Date of Patent: July 10, 2018Assignee: ARM LimitedInventors: Michael Alexander Kennedy, Anthony Jebson
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Publication number: 20170192915Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: ApplicationFiled: March 21, 2017Publication date: July 6, 2017Inventors: Michael Alexander KENNEDY, Anthony JEBSON
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Patent number: 9632957Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: GrantFiled: April 24, 2015Date of Patent: April 25, 2017Assignee: ARM LimitedInventors: Michael Alexander Kennedy, Anthony Jebson
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Patent number: 9430421Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.Type: GrantFiled: March 12, 2014Date of Patent: August 30, 2016Assignee: ARM LimitedInventors: Simon John Craske, Michael Alexander Kennedy, Andrew John Turner, Richard Anthony Lane
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Patent number: 9330035Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.Type: GrantFiled: May 23, 2013Date of Patent: May 3, 2016Assignee: ARM LimitedInventors: Anthony Jebson, Richard Roy Grisenthwaite, Michael Alexander Kennedy, Ian Michael Caulfield
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Publication number: 20150261700Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Inventors: Simon John Craske, Michael Alexander Kennedy, Andrew John Turner, Richard Anthony Lane
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Publication number: 20150227477Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: ApplicationFiled: April 24, 2015Publication date: August 13, 2015Inventors: Michael Alexander Kennedy, Anthony Jebson