Abstract: A crane (2), more particularly a mobile fast-erecting crane, having at least one supply connection to which a supply line (16), more particularly a power cable, can be connected, wherein the supply line can be wound on a cable drum (15), which can be mounted on a drum mount (10) on the crane, with the cable drum being mounted to rotate on a drum support frame (18), which has running gear (18) for moving the cable drum over the ground and which has releasable mounting means, shaped to match the drum mount of the crane, for separably mounting the drum support frame on the drum mount of the crane. The invention further relates to a cable drum unit for winding a supply line (16) of a crane (2).

Abstract: A method, computer device and computer program product are provided to modify a query that includes at least one temporal expression to identify a point in time at which the query is to be reevaluated. In the context of a method, a modified query is constructed from the query that includes at least one temporal expression. The modified query also identifies a next point in time at which the result of the query is able to change. The method also executes the modified query to determine a result of the query and to also determine the next point in time at which the result of the query is able to change. The method further includes scheduling the modified query to again be executed at the next point in time at which the result of the query is able to change.

Abstract: A method, apparatus, system and computer program product are provided for determining one or more current or future conditions regarding capacity and allocation of resources in an institution. The apparatus enables personnel to utilize predictive tools to identify in real-time or in the near future areas of capacity constraints within the institution. The apparatus includes a processor configured to analyze data which includes information associated with the institution. A portion of the data is generated in real-time during an actual time in which events occur. The processor is capable of using at least a portion of the data to identify current conditions or generate one or more predictions regarding conditions to occur in the future that are associated with resources and capacity of the institution. Also, the processor is capable of analyzing results of the predictions and allocating resources of the institution on the basis of the predicted results.

Abstract: A method for providing a patient quality monitor may include transforming patient data from a plurality of sources associated with different healthcare entities into a standard representation using a mapping to tag each piece of patient data to a common ontology, mapping the standard representation to corresponding Java class implementations, and mapping the corresponding Java class implementations to a relational database. A corresponding computer program product and apparatus are also provided.

Abstract: Systems, methods, apparatus, and computer program products are provided for monitoring quality metrics for patients in health care facilities. For example, in one embodiment, a monitoring server can monitor a set of quality metrics associated with a patient in a health care facility. During the monitoring process, the monitoring server can determine whether activities associated with the respective quality metrics have been or need to be performed, providing medical providers information in time to correct care documentation. The monitoring server can also cause display of graphics that indicate the results of such determinations.

Abstract: A system and method for training a clock signal are described. The method includes determining a first position of a clock signal by training the clock signal using a first test data, determining a final position of a clock signal by training the clock signal using a second test data, and using the offset between these positions to speed up subsequent trainings.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller that is able to effectively generate control signals for all four quadrants of phase control operation.

Abstract: A method, apparatus, system and computer program product are provided for determining one or more current or future conditions regarding capacity and allocation of resources in an institution. The apparatus enables personnel to utilize predictive tools to identify in real-time or in the near future areas of capacity constraints within the institution. The apparatus includes a processor configured to analyze data which includes information associated with the institution. A portion of the data is generated in real-time during an actual time in which events occur. The processor is capable of using at least a portion of the data to identify current conditions or generate one or more predictions regarding conditions to occur in the future that are associated with resources and capacity of the institution. Also, the processor is capable of analyzing results of the predictions and allocating resources of the institution on the basis of the predicted results.

Abstract: A network system comprises dynamic power management controllers respectively configured for usage in a Power Sourcing Equipment (PSE) and a Powered Device (PD) coupled by a network cable in a configuration that transfers power and communication signals from the PSE to the PD. The dynamic power management controllers are configured to communicate power management information over the network cable at a Transmission Control Protocol/Internet Protocol (TCP/IP) layer and/or a Media Access Control (MAC) layer.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller having first and second order integration. In some embodiments, the analog control circuit generates first and second control signals and controls the first control signal based on the sign of the second control signal and controls the second control signal based on the sign of the first control signal.

Abstract: A system and method for training a clock signal are described. The method includes determining a first position of a clock signal by training the clock signal using a first test data, determining a final position of a clock signal by training the clock signal using a second test data, and using the offset between these positions to speed up subsequent trainings.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller having first and/or second order integration.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller that is able to effectively generate control signals for all four quadrants of phase control operation.

Abstract: In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.

Abstract: A network device comprising an integrated circuit configured for coupling to lines between a network connector and an Ethernet physical layer (PHY) and comprising a diode bridge and protection circuitry integrated onto a common integrated circuit whereby parasitics in an energy discharge path and stress on the PHY and the diode bridge are reduced.

Abstract: A network system comprises dynamic power management controllers respectively configured for usage in a Power Sourcing Equipment (PSE) and a Powered Device (PD) coupled by a network cable in a configuration that transfers power and communication signals from the PSE to the PD. The dynamic power management controllers are configured to communicate power management information over the network cable at a Transmission Control Protocol/Internet Protocol (TCP/IP) layer and/or a Media Access Control (MAC) layer.

Abstract: A CML/ECL clock phase shifter device provides a 360.degree. phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMOS current switch which generates current signals having the amplitude adjustable with the control signal, which is a digital word. Differential pairs provide amplitude modulated current signals for the input clock and the variant of the input clock. Two MOS transmission networks selectively invert each amplitude modulated signal and sum the signals from each side on a load network. The phase control resolution is optimal over four quadrants for quadrature input clock signals.

Abstract: To reduce drift in a sampling clock for framed data, a phase detector senses the time difference between (i) the time when a reference mark for the framed data is received and (ii) the time when the nominal number of oversampling clock cycles between reference timing marks is received. This difference is output to a clock controller which chooses a phase change rate based thereon. This phase change rate is applied to an oversampling clock to continuously, progressively, change the phase of the oversampling clock in a sense which tends to reduce this phase error. The phase changing clock is divided down by a frequency divider to generate a sampling clock. The phase of the oversampling clock is changed by generating multiple, equally spaced, phases of the oversampling clock and progressively changing the selection of the active phase.

Abstract: A method and a circuit for simple clock recovery from multi-level at high transmission rates. The circuit is compatible with standard PLL-type clock recovery techniques for NRZ and generalized two-level signalling. The timing information is extracted from a single threshold crossing, irrespective of the number of levels (M) of the signal. This was verified to provide sufficient spectral information for the proper operation of a clock recovery PLL. The threshold may be programmed for various line codes.

Abstract: A programmable high frequency active filter comprises a plurality of basic building blocks connected in parallel. A basic building block includes a transistor pair connected in a differential amplifier configuration, an impedance connected between the emitters of the transistors and a switching block for applying the necessary bias current to the transistors. The transfer function of the filter is programmed with a digital word, the length of which determines the number of basic building blocks included in the configuration. In this way, the equivalent high frequency impedance of the filter is controlled by selecting the configuration and the value of the impedance of each building block.