Abstract: Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition different than the first. Prior to rinsing the portion of the workpiece surface, the portion is sequentially exposed to the first and second chemistries again. The first and second chemistries are removed from the portion, and, after sequentially exposing the portion to each of the first and second chemistries at least twice, and removing the first and second chemistries, the portion is rinsed and dried.

Abstract: Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition different than the first. Prior to rinsing the portion of the workpiece surface, the portion is sequentially exposed to the first and second chemistries again. The first and second chemistries are removed from the portion, and, after sequentially exposing the portion to each of the first and second chemistries at least twice, and removing the first and second chemistries, the portion is rinsed and dried.

Abstract: Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition different than the first. Prior to rinsing the portion of the workpiece surface, the portion is sequentially exposed to the first and second chemistries again. The first and second chemistries are removed from the portion, and, after sequentially exposing the portion to each of the first and second chemistries at least twice, and removing the first and second chemistries, the portion is rinsed and dried.

Abstract: The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material, semiconductor processing methods of forming an integrated circuit comprising a copper-containing conductive line, and cobalt-containing film cleaning solutions. In one implementation, a method of cleaning a surface of a cobalt-containing material includes forming a cobalt-containing material over a substrate. The surface of the cobalt-containing material is exposed to an aqueous mixture. The aqueous mixture has an acidic pH and comprises acetic acid, a multiprotic acid, and HF. Other aspects and implementations are contemplated.

Abstract: Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation, a semiconductor wafer backside is mechanically scrubbed to remove an undesired material prior to forming a final passivation layer over an oppositely facing semiconductor wafer frontside. In another implementation, the wafer backside is treated to remove the undesired material while treatment of the wafer frontside is restricted. In another implementation, the mechanical scrubbing of the wafer backside is conducted in connection with a polishing solution which is effective to facilitate removal of undesired material from the wafer backside. In a preferred implementation, dynamic random access memory storage capacitors are formed and the undesired material constitutes remnant polysilicon which adheres to the wafer backside during formation of a frontside capacitor storage node.

Abstract: A method for the post-etch cleaning of multi-level, damascene structures which minimizes, or substantially prevents, localized corrosion of underlying copper metallization comprises subjecting an intermediate structure in the fabrication of a multi-level, damascene structure, which structure includes an underlying copper metallization layer and an opening etched therein which exposes at least a portion of the underlying copper metallization layer, to an aqueous or acidic wash solution, in an environment substantially shielded from ambient light, to substantially remove any post-etch residues which may be present on the structure. In one embodiment, the aqueous or acidic wash solution has a nonzero static etch rate when applied to both the copper and conventional dielectric materials, e.g., silicon dioxide.

Abstract: A method of removing ruthenium silicide from a substrate surface which comprises exposing the ruthenium silicide surface to a solution containing chlorine and fluorine containing chemicals. In particular, said solution is designed to react with said ruthenium silicide film such that water-soluble reaction products are formed.

Abstract: An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid or salt thereof, and at least one antimicrobial agent resulting in a cleaning composition in which microbial growth is inhibited. Examples of suitable antimicrobial agents include a benzoic acid or salt such as potassium or ammonium benzoate, and sorbic acid or salt such as potassium sorbate. The composition is useful for cleaning a wafer and particularly for removing residual particles after a conductive layer has been planarized to a dielectric layer under the conductive layer in a chemical mechanical planarization of a semiconductor wafer with abrasive slurry particles, particularly after a CMP of copper or aluminum films.

Abstract: A post-CMP cleaning process includes brush cleaning a CMPed surface, followed by at least partially drying the CMPed surface, followed by spray cleaning the CMPed surface. A method of cleaning residue from registration alignment markings formed on a semiconductor substrate includes polishing a material within which the registration alignment markings are received with a polishing solution comprising a liquid and a solid, followed by brush cleaning a remaining outermost polished surface, followed by at least partially drying the polished surface, followed by spray cleaning the outermost polished surface. Other aspects and implementations are contemplated.

Abstract: A post-CMP cleaning process includes brush cleaning a CMPed surface, followed by at least partially drying the CMPed surface, followed by spray cleaning the CMPed surface. A method of cleaning residue from registration alignment markings formed on a semiconductor substrate includes polishing a material within which the registration alignment markings are received with a polishing solution comprising a liquid and a solid, followed by brush cleaning a remaining outermost polished surface, followed by at least partially drying the polished surface, followed by spray cleaning the outermost polished surface. Other aspects and implementations are contemplated.

Abstract: A method for the post-etch cleaning of multi-level, damascene structures which minimizes, or substantially prevents, localized corrosion of underlying copper metallization comprises subjecting an intermediate structure in the fabrication of a multi-level, damascene structure, which structure includes an underlying copper metallization layer and an opening etched therein which exposes at least a portion of the underlying copper metallization layer, to an aqueous or acidic wash solution, in an environment substantially shielded from ambient light, to substantially remove any post-etch residues which may be present on the structure. In one embodiment, the aqueous or acidic wash solution has a nonzero static etch rate when applied to both the copper and conventional dielectric materials, e.g., silicon dioxide.

Abstract: A method of removing organic particles from a registration mark on a semiconductor wafer. The method comprises providing a semiconductor wafer comprising at least one registration mark at least partially filled with organic particles. The at least one registration mark has a trench width from approximately 1.0 ?m to approximately 3.0 ?m. The semiconductor wafer is exposed to a cleaning solution comprising tetramethylammonium hydroxide and at least one surfactant, such as an acetylenic diol surfactant. The semiconductor wafer is exposed to an ultrasonic or megasonic vibrational energy. A semiconductor wafer previously subjected to a chemical mechanical planarization treatment and having a reduced amount of organic particles in a registration mark is also disclosed.

Abstract: A method of removing organic particles from a registration mark on a semiconductor wafer. The method comprises providing a semiconductor wafer comprising at least one registration mark at least partially filled with organic particles. The at least one registration mark has a trench width from approximately 1.0 ?m to approximately 3.0 ?m. The semiconductor wafer is exposed to a cleaning solution comprising tetramethylammonium hydroxide and at least one surfactant, such as an acetylenic diol surfactant. The semiconductor wafer is exposed to an ultrasonic or megasonic vibrational energy. A semiconductor wafer previously subjected to a chemical mechanical planarization treatment and having a reduced amount of organic particles in a registration mark is also disclosed.

Abstract: A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and removing at least a majority portion of the flocculated portion from the substrate. Applying solid abrasive material can include applying a CMP slurry or a polishing pad comprising abrasive material. Such a method can further include applying a surfactant comprising material to the substrate to assist in effectuating flocculation of the abrasive material. Such surfactant comprising material may be cationic which includes, for example, a quaternary ammonium substituted salt. Also, for example, the surfactant comprising material may be applied during polishing, brush scrubbing, pressure spraying, or buffing.

Abstract: Slurries used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such slurries. In one aspect of the invention, a planarizing slurry for planarizing a microelectronic-device substrate assembly is made by fracturing agglomerations of abrasive particles in a first slurry component into smaller agglomerations of abrasive particles or individual abrasive particles. The first slurry component can include water and the abrasive particles. The agglomerations of abrasive particles can be fractured into smaller units by imparting energy to the first slurry component before the first slurry component is mixed with a second slurry component. The agglomerations of abrasive particles are preferably fractured by imparting sonic energy to the first slurry component before it is mixed with the second slurry component. The agglomerations of abrasive particles in the first slurry component may also be fractured by ball milling or highly turbulent pumping.

Abstract: The invention relates to a communication system comprising a station (2) for charge metering of a connection point. This station comprises a monitoring circuit (7) for detecting a request for a connection set-up from the connection point (3), either for establishing the absence of a message after a given period of time, or for evaluating the contents of a message that has arrived from the connection point (3) after the request for a connection set-up has arrived, and for rejecting the request for a connection set-up if invalid parameters of the connection point (3) are established.