Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

Abstract: Provided are systems, methods, and media for simultaneous, non-atomic request processing of snooped operations of a broadcast scope within a SMP system. An example method includes detecting, by a first controller, based on a set of coherency resolution conditions, whether there are coherency resolution problems between two snooped operations. The method includes in response to detecting, by the first controller, that coherency resolution problems will not result, transmitting, from the first controller to a second controller, an indication signal indicating that coherency resolution problems will not result from the operation. The set of coherency resolution conditions includes: (a) detecting that a second operation of the two snooped operations operation is of a predetermined type, (b) detecting at time of snooping of the second operation that a directory state does not allow for exclusive data, and (c) detecting that the first controller has started committing to an update.

Abstract: Provided are systems, methods, and media for simultaneous, non-atomic request processing of snooped operations of a broadcast scope within a SMP system. An example method includes detecting, by a first controller, based on a set of coherency resolution conditions, whether there are coherency resolution problems between two snooped operations. The method includes in response to detecting, by the first controller, that coherency resolution problems will not result, transmitting, from the first controller to a second controller, an indication signal indicating that coherency resolution problems will not result from the operation. The set of coherency resolution conditions includes: (a) detecting that a second operation of the two snooped operations operation is of a predetermined type, (b) detecting at time of snooping of the second operation that a directory state does not allow for exclusive data, and (c) detecting that the first controller has started committing to an update.

Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

Abstract: A hierarchical cache architecture that reduces traffic on a main memory bus while overcoming the disadvantages of prior systems. The architecture includes a plurality of level one caches that are of the store through type, each level one cache is associated with a processor and may be incorporated into the processor. Subsets (or "clusters") of processors, along with their associated level one caches, are formed and a level two cache is provided for each cluster. Each processor-level one cache pair within a cluster is coupled to the cluster's level two cache through a dedicated bus. By configuring the processors and caches in this manner, not only is the speed advantage normally associated with the use of cache memory realized, but the number of memory bus accesses is reduced without the disadvantages associated with the use of store in type caches at level one and without the disadvantages associated with the use of a shared cache bus.