Patents by Inventor Michael Andrew Brian Parkes

Michael Andrew Brian Parkes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10185653
    Abstract: An integrated system for transactionally managing main memory and storage devices derived from the interfaces and methodologies historically associated with dynamic memory allocation. The methodology has a wide range of applicability including areas such as hardware storage devices (i.e. firmware), operating system internals (i.e. file systems) and end-user software systems.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 22, 2019
    Inventors: Michael Andrew Brian Parkes, Gregory Michael Parkes
  • Publication number: 20170010834
    Abstract: An integrated system for transactionally managing main memory and storage devices derived from the interfaces and methodologies historically associated with dynamic memory allocation. The methodology has a wide range of applicability including areas such as hardware storage devices (i.e. firmware), operating system internals (i.e. file systems) and end-user software systems.
    Type: Application
    Filed: February 29, 2016
    Publication date: January 12, 2017
    Inventors: Michael Andrew Brian Parkes, Gregory Michael Parkes
  • Patent number: 6295608
    Abstract: An invention for reassigning data elements of an application to cache lines to decrease the occurrence of cache line faults is described. First, an application is executed and used in a typically manner. While the application is running, data is collected concerning the loading and storing of data elements. This collection process creates a massive volume of data that is then processed to determine correlations between the loading and storing pairs of elements within each of the application's data structures. These correlations provide a mechanism for weighing the probability of pairs of intra-structure data elements being accessed in sequence, which is best accomplished when the data elements are within a single cache line. A set of simultaneous equations describe the probabilities using the data recording the correlations. These equations are then solved using commonly known linear programming techniques to derive a suggested ordering of data structures.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 25, 2001
    Assignee: Microsoft Corporation
    Inventors: Michael Andrew Brian Parkes, Barry Michael Nolte, Douglas Stewart Boa
  • Patent number: 6189069
    Abstract: An invention for optimizing the logging of data elements to a hardware device is described. Using this invention, a large stream of data can be written to a hardware device at a rate that approaches the limits of the physical characteristics of the hardware device. To achieve this efficiency, the performance of a logging operation is divided between a data source and a data logging software processes which operate in different threads or processes. The data source collects pieces of data to be written to the hardware device into a larger buffer retrieved from a pool of empty buffers. When a buffer becomes full, the buffer is placed at the end of a full buffer queue. The data logger, operating asynchronously, retrieves a full buffer from the queue and then writes the data to the hardware. In this fashion, the hardware data logging device is able to perform optimally while creating or expanding the file.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: February 13, 2001
    Assignee: Microsoft Corporation
    Inventors: Michael Andrew Brian Parkes, Barry Michael Nolte, Douglas Stewart Boa