Patents by Inventor Michael Andrew Derenge

Michael Andrew Derenge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method using multiple layer annealing cap for fabricating group III-nitride semiconductor device structures and devices formed thereby
    Patent number: 7977224
    Abstract: A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: July 12, 2011
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Carl Emmett Hager, IV, Michael Andrew Derenge, Kenneth Andrew Jones
  • Method Using Multiple Layer Annealing Cap for Fabricating Group III-Nitride Semiconductor Device Structures and Devices Formed Thereby
    Publication number: 20100133656
    Abstract: A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 3, 2010
    Applicant: United States Government as represented by the Secretary of the Army
    Inventors: CARL EMMETT HAGER, IV, MICHAEL ANDREW DERENGE, KENNETH ANDREW JONES
  • Method for fabricating group III-nitride high electron mobility transistors (HEMTs)
    Publication number: 20090233414
    Abstract: A method of manufacturing a transistor comprises providing a wafer; growing a group III-nitride semiconductor material on a first side of the wafer; creating alignment marks on a second side of the wafer, the second side of the wafer being positioned opposite to the first side of the wafer; etching the first side of the wafer to create free standing walls on the first side of the wafer; growing pendeo-epitaxy regrowth regions on the free standing walls; and forming mesa isolated regions in the pendeo-epitaxy regrowth regions. The method may further comprise positioning a patterned mask on the first side of the wafer; and aligning the patterned mask with the alignment marks located on the second side of the wafer.
    Type: Application
    Filed: October 20, 2005
    Publication date: September 17, 2009
    Inventors: Pankaj B. Shah, Michael Andrew Derenge