Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).

Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).

Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).

Abstract: One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.

Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).

Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

Abstract: One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.

Abstract: The input/output expansion system (“I/O expansion system”) for an external or main computing unit includes a rack; at least one I/O expansion module mounted to the rack, the I/O expansion module comprising at least one I/O circuit card; a utilities control module mounted to the rack, the utilities control module being configured to receive a command from the external computer unit and generating a signal in response to the command for distribution to at least one I/O expansion module; and expansion power chassis mounted to the rack, the an expansion power chassis being electrically connected to a power source and being configured to distribute the power to the at least one I/O expansion module and the utilities control module.

Abstract: The invention provides EMI cable shield termination apparatus. The apparatus includes (a) a cable exit panel coupled to a first electronic system and (b) one or more clamps coupled to the exit panel. The exit panel serves as an interface for one or more cables coupled to the first electronic system; the clamps provide mechanical coupling, and EMI shielding, for the cables to that interface. The exit panel couples to electrical ground such as through connection to the chassis of the first electronic system. The clamps also couple to ground through connection with the exit panel. Preferably, one end of the cables attaches to the clamps, at the interface formed by the exit panel, and the other end of the cables attach to respective ferrules coupled to a second electronics system. Beneficially, the apparatus reduces EMI effects generated from the first electronic system and coupled into the second electronic system.

Abstract: A shielded cable assembly contains one or more hardpoints that resist damage arising from possible collapse of the shielded cable assembly under strong compressional forces that are exerted by a clamp assembly in the form of a separable block having first and second opposed members. The hardpoint contains a conduit that protects a data transfer line or cable bundle by compressing electromagnetic shielding between the conduit and the clamp assembly. Cable electromagnetic shielding may be exposed over a selected hardpoint for use as needed in a particular application.

Abstract: A shielded cable assembly contains a hardpoint that resists damage arising from possible collapse of the shielded cable assembly under strong compressional forces that are exerted by a clamp assembly in the form of a separable block having first and second opposed members. The hardpoint contains a conduit that protects a data transfer line or cable bundle by compressing electromagnetic shielding between the conduit and the clamp assembly.

Abstract: The invention provides EMI cable shield termination apparatus. The apparatus includes (a) a cable exit panel coupled to a first electronic system and (b) one or more clamps coupled to the exit panel. The exit panel serves as an interface for one or more cables coupled to the first electronic system; the clamps provide mechanical coupling, and EMI shielding, for the cables to that interface. The exit panel couples to electrical ground such as through connection to the chassis of the first electronic system. The clamps also couple to ground through connection with the exit panel. Preferably, one end of the cables attaches to the clamps, at the interface formed by the exit panel, and the other end of the cables attach to respective ferrules coupled to a second electronics system. Beneficially, the apparatus reduces EMI effects generated from the first electronic system and coupled into the second electronic system.

Abstract: A shielded cable assembly contains one or more hardpoints that resist damage arising from possible collapse of the shielded cable assembly under strong compressional forces that are exerted by a clamp assembly in the form of a separable block having first and second opposed members. The hardpoint contains a conduit that protects a data transfer line or cable bundle by compressing electromagnetic shielding between the conduit and the clamp assembly. Cable electromagnetic shielding may be exposed over a selected hardpoint for use as needed in a particular application.

Abstract: A shielded cable assembly contains a hardpoint that resists damage arising from possible collapse of the shielded cable assembly under strong compressional forces that are exerted by a clamp assembly in the form of a separable block having first and second opposed members. The hardpoint contains a conduit that protects a data transfer line or cable bundle by compressing electromagnetic shielding between the conduit and the clamp assembly.

Abstract: The input/output expansion system (“I/O expansion system”) for an external or main computing unit includes a rack; at least one I/O expansion module mounted to the rack, the I/O expansion module comprising at least one I/O circuit card; a utilities control module mounted to the rack, the utilities control module being configured to receive a command from the external computer unit and generating a signal in response to the command for distribution to at least one I/O expansion module; and expansion power chassis mounted to the rack, the an expansion power chassis being electrically connected to a power source and being configured to distribute the power to the at least one I/O expansion module and the utilities control module.

Abstract: In a computer system having SDRAM memory banks that use a full burst read-modify-write operation as the sole mode for conducting memory operations, by selectively truncating the memory operation, it is possible to simulate either a burst read operation or a burst write operation. In a truncated read operation, a full read portion of the memory operation is performed. The tag is read with the first data line and is updated while the remaining lines of the burst are read. The tag is written using the write portion, but then the burst operation is aborted or truncated by issuing a precharge command to abort the write after the first line of the write is completed. This saves three clock periods out of a cycle of seventeen clock periods. A truncated write operation is similar to the read operation. A full burst read is started to retrieve the tag, which is stored to the first line, but the burst is truncated after the first line has been read.

Abstract: A method and system for preserving the state of memory while a memory subsystem is scan tested. In certain situations, it is desirable to scan test a memory subsystem. Scan testing is accomplished by causing the registers in a memory controller to form at least one ring. Then, register values are shifted through the ring and analyzed. Clocks within the memory controller must be stopped before scan testing can be conducted. Accordingly, the memory controller is unable to provide refresh requests to the memory during testing. Therefore, the memory controller places the memory in a self-refresh mode during scanning. While in the self-refresh mode, the memory automatically refreshes itself but does not respond to read or write requests. Once scanning is completed, the memory controller takes the memory out of self-refresh mode.