Patents by Inventor Michael Ang
Michael Ang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120881Abstract: A clock device including: an LC network comprising: a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.Type: ApplicationFiled: November 13, 2023Publication date: April 11, 2024Inventors: Michael A. Ang, Alan C. Rogers
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Publication number: 20240113923Abstract: A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.Type: ApplicationFiled: June 30, 2023Publication date: April 4, 2024Inventors: Michael A. Ang, Alan C. Rogers
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Patent number: 11817824Abstract: A clock device includes an LC network that has a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.Type: GrantFiled: September 29, 2022Date of Patent: November 14, 2023Assignee: Analog Bits Inc.Inventors: Michael A. Ang, Alan C. Rogers
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Patent number: 11729029Abstract: A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.Type: GrantFiled: November 12, 2021Date of Patent: August 15, 2023Assignee: Analog Bits Inc.Inventors: Michael A. Ang, Alan C. Rogers
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Publication number: 20230246883Abstract: A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.Type: ApplicationFiled: February 3, 2022Publication date: August 3, 2023Applicant: Analog Bits, Inc.Inventors: Alan C. Rogers, Michael A. Ang
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Publication number: 20230061840Abstract: A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.Type: ApplicationFiled: November 12, 2021Publication date: March 2, 2023Inventors: Michael A. Ang, Alan C. Rogers
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Publication number: 20210122223Abstract: Vehicle platforms, and systems, subsystems, and components thereof are described. A self-contained vehicle platform or chassis incorporating substantially all of the functional systems, subsystems and components (e.g., mechanical, electrical, structural, etc.) necessary for an operative vehicle. Functional components may include at least energy storage/conversion, propulsion, suspension and wheels, steering, crash protection, and braking systems. Functional components are standardized such that vehicle platforms may be interconnected with a variety of vehicle body designs (also referred to in the art as “top hats”) with minimal or no modification to the functional linkages (e.g., mechanical, structural, electrical, etc.) therebetween. Configurations of functional components are incorporated within the vehicle platform such that there is minimal or no physical overlap between the functional components and the area defined by the vehicle body.Type: ApplicationFiled: January 6, 2021Publication date: April 29, 2021Applicant: Canoo Inc.Inventors: Daniel McCarron, Alexi Charbonneau, William Rohr, Charles Garmel, Felix Haeusler, Nathaniel Rosso, John Mason, Mayurkumar Agrawal, Phillip Weicker, Sohel Merchant, Naesung Lyu, Michael Ang, Jeffrey Walsh
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Publication number: 20210070123Abstract: A suspension system configured to sit substantially within the profile of a vehicle platform such that none of the elements extend substantially above the plane of the vehicle platform. The suspension system may utilize an adaptable transverse leaf spring in combination with other suspension elements, to allow the vehicle platform to maintain a generally flat profile and accommodate a variety of different body like structures while maintaining the desired roll and ride stability stiffness.Type: ApplicationFiled: September 9, 2020Publication date: March 11, 2021Applicant: Canoo Inc.Inventors: Felix Haeusler, Nathaniel Rosso, Michael Ang, Jeffrey Walsh, Alexi Charbonneau, Brian Austin, Charles Garmel, John Mason, Daniel McCarron, Naesung Lyu
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Publication number: 20200369140Abstract: Vehicle platforms, and systems, subsystems, and components thereof are described. A self-contained vehicle platform or chassis incorporating substantially all of the functional systems, subsystems and components (e.g., mechanical, electrical, structural, etc.) necessary for an operative vehicle. Functional components may include at least energy storage/conversion, propulsion, suspension and wheels, steering, crash protection, and braking systems. Functional components are standardized such that vehicle platforms may be interconnected with a variety of vehicle body designs (also referred to in the art as “top hats”) with minimal or no modification to the functional linkages (e.g., mechanical, structural, electrical, etc.) therebetween. Configurations of functional components are incorporated within the vehicle platform such that there is minimal or no physical overlap between the functional components and the area defined by the vehicle body.Type: ApplicationFiled: May 20, 2020Publication date: November 26, 2020Applicant: Canoo Inc.Inventors: Daniel McCarron, Alexi Charbonneau, William Rohr, Charles Garmel, Felix Haeusler, Nathaniel Rosso, John Mason, Mayurkumar Agrawal, Phillip Weicker, Sohel Merchant, Naesung Lyu, Michael Ang, Jeffrey Walsh
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Patent number: 8742957Abstract: A method is described for encoding N variables onto less than 2N channels by forming a respective signal for each of the channels by combining inverted and/or non inverted forms of the variables, such that, each of the N variables is balanced across the channels, and, combination on any particular channel is not the polar opposite of a combination on any other channel.Type: GrantFiled: December 15, 2011Date of Patent: June 3, 2014Assignee: Analog Bits, Inc.Inventors: Michael A. Ang, Alan C. Rogers
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Patent number: 8583895Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.Type: GrantFiled: January 22, 2004Date of Patent: November 12, 2013Assignee: Nytell Software LLCInventors: Eino Jacobs, Michael Ang
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Publication number: 20120154183Abstract: A method is described for encoding N variables onto less than 2N channels by forming a respective signal for each of the channels by combining inverted and/or non inverted forms of the variables, such that, each of the N variables is balanced across the channels, and, combination on any particular channel is not the polar opposite of a combination on any other channel.Type: ApplicationFiled: December 15, 2011Publication date: June 21, 2012Applicant: ANALOG BITS, INC.Inventors: Michael A. Ang, Alan C. Rogers
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Publication number: 20040181648Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.Type: ApplicationFiled: January 22, 2004Publication date: September 16, 2004Inventors: Eino Jacobs, Michael Ang
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Patent number: 6704859Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.Type: GrantFiled: August 4, 1998Date of Patent: March 9, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Eino Jacobs, Michael Ang
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Patent number: 6608506Abstract: A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit.Type: GrantFiled: March 20, 2002Date of Patent: August 19, 2003Assignee: Sun Microsystems, Inc.Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, Sai V. Vishwanthaiah
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Publication number: 20020158674Abstract: A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit.Type: ApplicationFiled: March 20, 2002Publication date: October 31, 2002Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, Sai V. Vishwanthaiah
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Patent number: 6420913Abstract: A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit.Type: GrantFiled: September 20, 1999Date of Patent: July 16, 2002Assignee: Sun Microsystems, Inc.Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, Sai V. Vishwanthaiah
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Patent number: 6411131Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently vary small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.Type: GrantFiled: May 21, 1999Date of Patent: June 25, 2002Assignee: Sun Microsystems, Inc.Inventors: Michael A. Ang, Jonathan E. Starr
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Patent number: 6366139Abstract: A method may be provided which controls the output impedance of a driver which includes within the driver an impedance circuit and a slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a method also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.Type: GrantFiled: June 7, 1999Date of Patent: April 2, 2002Assignee: Sun Microsystems, Inc.Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, Sai V. Vishwanthaiah
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Patent number: 6339351Abstract: A driver may be provided which controls output impedance of a driver which includes within the driver an impedance circuit and slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.Type: GrantFiled: June 7, 1999Date of Patent: January 15, 2002Assignee: Sun Microsystems, Inc.Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, Sai V. Vishwanthaiah