Abstract: The present invention relates to a prefabricated cable, to a cable plug connector arrangement, and to an electrical plug connection. A prefabricated cable (1) has a shielding foil (4), a shielding braid (5) which surrounds the shielding foil (4), and a cable sheath (6) which surrounds the shielding braid (5). The shielding braid (5) is exposed from the cable sheath (6) at a plug-side end (8) of the prefabricated cable (1). The shielding foil (4) has a dielectric foil (9) made of a dielectric material, and a metal coating (101, 102) on an outer lateral surface and on an inner lateral surface of the dielectric foil (9). The metal coating (101) on the outer lateral surface is electrically conductively connected to the metal coating (102) on the inner lateral surface in a plug-side end region (11) of the shielding foil (4) via at least one electrically conductive connection (12).

Abstract: A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode, discharging the read capacity over the active material of the memory cell, and determining the memory state of the memory cell in dependence on a change of the voltage during the discharge of the read capacity.

Abstract: An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

Abstract: The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.

Abstract: According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the first potential, thereby generating a memory state sensing current flowing through the resistivity changing memory cell; controlling the strength of the second potential in dependence on the strength of the memory state sensing current such that the strength of the memory state sensing current is kept constant.

Abstract: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Abstract: A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of resistivity changing memory cells, the at least one resistivity changing reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal.

Abstract: According to one embodiment of the present invention, a memory device includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, and a plurality of select devices. Each current path output terminal is connected to at least one different current path output terminal via at least one select device.

Abstract: A memory device and a method of operating a memory device is disclosed. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2n with n being a non-zero integer, and a circuit or device for combining the levels of at least two of the memory cells for write and read operations into a set of combined states and for transforming at least a subset of 2n combinations of the set of combined states into n two-level data bits.

Abstract: An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line of the plurality of bit lines to select a row of storage devices, and the second voltage is applied to each of further lines except for a further line being connected to the storage devices of the selected column.

Abstract: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

Abstract: A memory device and a method of operating a memory device is disclosed. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2n with n being a non-zero integer, and a circuit or device for combining the levels of at least two of the memory cells for write and read operations into a set of combined states and for transforming at least a subset of 2n combinations of the set of combined states into n two-level data bits.

Abstract: A memory device, and method of operating the same, wherein the device includes resistive memory cells being switched between a low-resistive state and a high-resistive state; an evaluation unit, being coupled to a resistive memory cell to determine a resistive state of the resistive memory cell; and a voltage regulation circuit, being coupled to the resistive memory cell and to the evaluation unit. The voltage being applied to the resistive memory cell is regulated with respect to a target voltage.

Abstract: A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode, discharging the read capacity over the active material of the memory cell, and determining the memory state of the memory cell in dependence on a change of the voltage during the discharge of the read capacity.

Abstract: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

Abstract: The invention relates to a memory circuit comprising a resistive memory cell having a selection transistor and a resistive memory element connected in series, wherein the resistive memory element is coupled to a plate potential; and a control circuit to control the selection transistor by means of an activation signal a pre-charge circuit coupled with a node between the selection transistor and the resistive memory element and to apply a compensation potential to the node; wherein the control circuit controls the pre-charge circuit so that a compensation potential is applied to the node prior to a level transition of the activation signal.

Abstract: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Abstract: The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.