Abstract: An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Abstract: An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Abstract: An approach is in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and creates a thermal relief pattern that includes thermal relief shapes that identify conductive material voids on a power plane layer to exclude substantially conductive material. The dynamic thermal relief generator determines that one of the conductive material voids affects one or more proximate signal tracks and, in turn, automatically adjusts the thermal relief pattern accordingly.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.