Patents by Inventor Michael Anthony Lamson
Michael Anthony Lamson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9030216Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.Type: GrantFiled: April 10, 2012Date of Patent: May 12, 2015Assignee: Texas Instruments IncorporatedInventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
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Publication number: 20120194208Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
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Patent number: 8174276Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.Type: GrantFiled: May 22, 2009Date of Patent: May 8, 2012Assignee: Texas Instruments IncorporatedInventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
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Publication number: 20090289648Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.Type: ApplicationFiled: May 22, 2009Publication date: November 26, 2009Inventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
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Patent number: 7132845Abstract: In a method and system for testing a test sample (190), a simulation program (130) is used to augment test results provided by a legacy test system (101). The legacy test system (101) includes a measuring device (110) providing a test input (112) to the test sample (190) and receiving a test output (116) from the test sample (190) in response to the test input (112). The simulation program (130) simulates the test sample (190) by predicting a simulated output (134) of the test sample (190) in response to receiving a simulated input (132). A plurality of simulated failures is simulated in the simulation program (130), with each simulated failure generating a corresponding simulated output. The simulation program (130) includes a model (140) for the measuring device (110), the model (140) providing the simulated input (132). A comparator (160) compares the test output (134) with the simulated output (134) to determine a match.Type: GrantFiled: August 19, 2005Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Michael Anthony Lamson, Jay Michael Lawyer, Roger Joseph Stierman
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Patent number: 6030859Abstract: A lead frame for a semiconductor IC device has a pair of common elongated leads and first and second groups of slender leads arranged on opposite sides of the common elongated leads and generally extending transverse to the common elongated leads. The common elongated leads have as their integral parts slender leads extending therefrom generally transverse thereto and substantially linear extensions from both ends of the common elongated leads. The linear extensions serve to firmly support a semiconductor chip to be packaged along with parts of the leads. The common elongated leads may further have as their integral parts projections extending from their sides for enhancement of the heat dissipation capability. A semiconductor chip may have bonding pads arranged thereon such that bonding wires and the common elongated leads do not cross each other for electrical connection between the common elongated leads and bonding pads of the semiconductor chip.Type: GrantFiled: March 14, 1997Date of Patent: February 29, 2000Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Ichiro Anjoh, Gen Murakami, Michael Anthony Lamson, Katherine Gail Heinen
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Patent number: 5994169Abstract: A lead frame (10) is connected over an integrated circuit (40) by adhesives (42) and (44). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on adhesives (42) and (44) to provide noise shielding for the integrated circuit (40).Type: GrantFiled: January 23, 1998Date of Patent: November 30, 1999Assignee: Texas Instruments IncorporatedInventors: Michael Anthony Lamson, Katherine Gail Heinen
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Patent number: 5840599Abstract: A process for manufacturing a lead frame (10) connected over an integrated circuit (40) by adhesives (42) and (44). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on adhesives (42) and (44) to provide noise shielding for the integrated circuit (40).Type: GrantFiled: October 27, 1994Date of Patent: November 24, 1998Assignee: Texas Instruments IncorporatedInventors: Michael Anthony Lamson, Katherine Gail Heinen
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Patent number: 5648299Abstract: A lead frame for a semiconductor IC device has a pair of common elongated leads and first and second groups of slender leads arranged on opposite sides of the common elongated leads and generally extending transverse to the common elongated leads. The common elongated leads have as their integral parts slender leads extending therefrom generally transverse thereto and substantially linear extensions from both ends of the common elongated leads. The linear extensions serve to firmly support a semiconductor chip to be packaged along with parts of the leads. The common elongated leads may further have as their integral parts projections extending from their sides for enhancement of the heat dissipation capability. A semiconductor chip may have bonding pads arranged thereon such that bonding wires and the common elongated leads do not cross each other for electrical connection between the common elongated leads and bonding pads of the semiconductor chip.Type: GrantFiled: June 4, 1996Date of Patent: July 15, 1997Assignees: Hitachi, Ltd., Texas Instruments, Inc.Inventors: Ichiro Anjoh, Gen Murakami, Michael Anthony Lamson, Katherine Gail Heinen