Patents by Inventor Michael Aquilino
Michael Aquilino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11101364Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.Type: GrantFiled: March 8, 2019Date of Patent: August 24, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: George R. Mulfinger, Hong Yu, Man Gu, Jianwei Peng, Michael Aquilino
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Patent number: 10930549Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: GrantFiled: September 17, 2019Date of Patent: February 23, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
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Patent number: 10833160Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.Type: GrantFiled: April 17, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
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Publication number: 20200335591Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.Type: ApplicationFiled: April 17, 2019Publication date: October 22, 2020Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
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Publication number: 20200287019Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.Type: ApplicationFiled: March 8, 2019Publication date: September 10, 2020Inventors: George R. Mulfinger, Hong Yu, Man Gu, Jianwei Peng, Michael Aquilino
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Patent number: 10644156Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.Type: GrantFiled: March 12, 2018Date of Patent: May 5, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Xusheng Wu, Haigou Huang
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Publication number: 20200013672Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Jinsheng GAO, Daniel JAEGER, Chih-Chiang CHANG, Michael AQUILINO, Patrick CARPENTER, Junsic HONG, Mitchell RUTKOWSKI, Haigou HUANG, Huy CAO
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Patent number: 10522639Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: June 29, 2019Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10460986Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: GrantFiled: January 29, 2018Date of Patent: October 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
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Publication number: 20190326408Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: ApplicationFiled: June 29, 2019Publication date: October 24, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10418455Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: September 26, 2017Date of Patent: September 17, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Publication number: 20190280114Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.Type: ApplicationFiled: March 12, 2018Publication date: September 12, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Xusheng Wu, Haigou Huang
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Publication number: 20190237363Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: ApplicationFiled: January 29, 2018Publication date: August 1, 2019Inventors: Jinsheng GAO, Daniel JAEGER, Chih-Chiang CHANG, Michael AQUILINO, Patrick CARPENTER, Junsic HONG, Mitchell RUTKOWSKI, Haigou HUANG, Huy CAO
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Patent number: 10340142Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.Type: GrantFiled: March 12, 2018Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Jiehui Shu, Pei Liu, Jinping Liu
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Patent number: 10325819Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.Type: GrantFiled: March 13, 2018Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Jessica Dechene, Huy Cao, Mitchell Rutkowski, Haigou Huang
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Patent number: 10269654Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.Type: GrantFiled: February 6, 2018Date of Patent: April 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Jessica Dechene, Huy Cao, Mitchell Rutkowski, Haigou Huang
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Publication number: 20190097015Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Applicant: GLOBALFOUDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10204797Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.Type: GrantFiled: February 6, 2018Date of Patent: February 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Junsic Hong, Jessica Dechene, Haigou Huang
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Patent number: 9905473Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins. A sacrificial cobalt layer is used to backfill the cavities formed by etching the interlayer dielectric prior to forming a functional gate.Type: GrantFiled: May 18, 2017Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Vimal Kamineni, Michael Aquilino