Patents by Inventor Michael Armacost

Michael Armacost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101555
    Abstract: The present invention is directed to urea compounds which are agonists of orexin receptors. The present invention is also directed to uses of the compounds described herein in the potential treatment or prevention of neurological and psychiatric disorders and diseases in which orexin receptors are involved. The present invention is also directed to compositions comprising these compounds. The present invention is also directed to uses of these compositions in the potential prevention or treatment of such diseases in which orexin receptors are involved.
    Type: Application
    Filed: December 14, 2021
    Publication date: March 28, 2024
    Applicant: Merck Sharp & Dohme LLC
    Inventors: Kira A. Armacost, Maria Irina Chiriac, Danielle M. Hurzy, Jeffrey C. Kern, Jian Liu, Peter J. Manley, Philippe Nantermet, Vanessa L. Rada, Michael T. Rudd, Craig A. Stump
  • Publication number: 20240067657
    Abstract: The present invention relates to novel Amido-Substituted Heterocycle Compounds of Formula (I): and pharmaceutically acceptable salts thereof, wherein R1, R2, R3, R4, R7, and R8 are as defined herein. The present invention also relates to compositions comprising at least one Amido-Substituted Heterocycle Compound, and methods of using the Amido-Substituted Heterocycle Compounds for treating or preventing a herpesvirus infection in a patient.
    Type: Application
    Filed: December 21, 2021
    Publication date: February 29, 2024
    Applicant: Merck Sharp & Dohme LLC
    Inventors: Kira A. Armacost, Richard Thaddeus Berger, Jr., Andrew J. Cooke, Christopher Douglas Cox, Brendan M. Crowley, Marc Labroli, Michael Aaron Plotkin, Izzat Tiedje Raheem, Anthony W. Shaw, Kelly-Ann S. Schlegel, Jason W. Skudlarek, Ling Tong
  • Publication number: 20090317628
    Abstract: In one aspect, a method is provided which includes (1) providing a substrate including a photoresist layer and an additional layer which may be a potential source of contaminants, and (2) preventing a release of contaminants from the additional layer, wherein preventing the release of contaminants from the additional layer protects the photoresist layer from exposure to contaminants from the additional layer. Numerous other aspects are provided.
    Type: Application
    Filed: July 20, 2008
    Publication date: December 24, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Mehul Naik, Keisuke Mizuuchi, Huixiong Dai, Michael Armacost, Li-Qun Xia
  • Publication number: 20090117745
    Abstract: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer and/or a hardmask layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in an etch reactor, flowing a gas mixture containing SiF4 gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer using a plasma formed from the gas mixture.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 7, 2009
    Inventors: SIYI LI, Michael Armacost
  • Publication number: 20080102638
    Abstract: The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.
    Type: Application
    Filed: October 24, 2007
    Publication date: May 1, 2008
    Inventors: MEHUL NAIK, Suketu Parikh, Michael Armacost
  • Publication number: 20060246683
    Abstract: A method is provided that includes (1) receiving information about a substrate processed within a low K dielectric deposition subsystem from an integrated inspection system of the low K dielectric deposition subsystem; (2) determining an etch process to perform within an etch subsystem based at least in part on the information received from the inspection system of the low K dielectric deposition subsystem; and (3) directing the etch subsystem to etch at least one low K dielectric layer on the substrate based on the etch process. Other methods, systems, apparatus, data structures and computer program products are provided.
    Type: Application
    Filed: June 21, 2006
    Publication date: November 2, 2006
    Inventors: Judon Pan, Michael Armacost, Hoiman Hung, Hongwen Li, Arulkumar Shanmugasundram, Moshe Sarfaty, Dimitris Lymberopoulos, Mehul Naik
  • Publication number: 20050014361
    Abstract: Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.
    Type: Application
    Filed: May 18, 2004
    Publication date: January 20, 2005
    Inventors: Son Nguyen, Michael Armacost, Mehul Naik, Girish Dixit, Ellie Yieh
  • Patent number: 6342722
    Abstract: An integrated circuit and method of making the integrated circuit. Air gaps are formed between surfaces of current-conducting lines that face one another and dielectric material disposed between these surfaces of the current-conducting lines. A liner material is applied to these surfaces of the current-conducting lines and, after the dielectric material is introduced between the current-conducting lines, the liner material is removed, for example by etching, leaving air gaps between the current-conducting lines and the dielectric material. These air gaps eliminate or greatly reduce the effect of capacitive currents across the dielectric material between the current-conducting lines.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: January 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, Peter D. Hoh, David V. Horak, Richard S. Wise
  • Patent number: 6232222
    Abstract: A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: May 15, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, Richard A. Conti, Jeffrey P. Gambino, Jeremy K. Stephens
  • Patent number: 6228279
    Abstract: By providing a photoresist material with a protective polymer layer during the etching of an organic anti-reflective coating, undue damage to the photoresist material can be avoided during opening of the anti-reflective coating without the need for an oxidant. The preferred polymer chemistry system for producing such a result includes a fluorohydrocarbon-containing polymer mixture with a strong source of CF3, preferably C2F6. The etchant also includes a source of hydrogen selected from CH3F, C2HF5, or CH2F2, and a diluent selected from Ar, He or N2.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, Peter Hoh, Richard S. Wise, Wendy Yan
  • Patent number: 6090722
    Abstract: A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: July 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, Sandra G. Malhotra, Tina Wagner, Richard Wise
  • Patent number: 5766968
    Abstract: A method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 16, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, A. Richard Baker, Jr., Wayne Stuart Berry, Daniel Arthur Carl, Donald McAllpine Kenney, Thomas John Licata
  • Patent number: 5466626
    Abstract: The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, A. Richard Baker, Jr., Wayne S. Berry, Daniel A. Carl, Donald M. Kenney, Thomas J. Licata