Abstract: An apparatus including a memory, and a processor coupled to the memory is provided to, obtain information indicating plural rules, a rule among the rules to specify a plurality of conditions including at least one monetary threshold condition and at least one corresponding condition for the monetary threshold condition; obtain information about a sequence of monetary amounts; and execute a process to transform the rules into operator data objects that define a logic common to the rules to control allocation of the sequence of monetary amounts to at least one category. The operator data objects form a network of operator data objects to simulate, according to the defined logic common to the rules, allocation of the sequence of monetary amounts in response to passing in sequence the information about the monetary amounts among the network of operator data objects.

Abstract: An apparatus including a memory, and a processor coupled to the memory is provided to, obtain information indicating plural rules, a rule among the rules to specify a plurality of conditions including at least one monetary threshold condition and at least one corresponding condition for the monetary threshold condition; obtain information about a sequence of monetary amounts; and execute a process to transform the rules into operator data objects that define a logic common to the rules to control allocation of the sequence of monetary amounts to at least one category. The operator data objects form a network of operator data objects to simulate, according to the defined logic common to the rules, allocation of the sequence of monetary amounts in response to passing in sequence the information about the monetary amounts among the network of operator data objects.

Abstract: A circuit and method for equalization of a communication signal received over a communication system transmission line using switched filter characteristics. Equalization for frequency-independent and frequency-dependent attenuation of the communication signal is accomplished with a linear equalization channel which includes an input biasing circuit which provides a common input signal to two parallel amplifier paths. One path includes a wideband, fixed-gain, frequency-independent amplifier stage. The other path is a wideband multiplier amplifier stage in series with a wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic. The outputs of the fixed-gain wideband frequency-independent amplifier stage and wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic are both tied in common to the input of a wideband gain buffer amplifier stage, which has a switchable high-frequency boost frequency response characteristic.

Abstract: A voltage-to current (V-to-I) converter circuit for use in combination with a current-controlled oscillator (ICO) to form a voltage-controlled oscillator (VCO), wherein the V-to-I converter circuit provides a current to the ICO while this current ranges itself corresponding to the process, supply voltage, and temperature needs of the ICO, thus allowing a more stabilized ICO and VCO. In one embodiment, the V-to-I circuit allows for independent adjustability to compensate for each quantity of required process, supply voltage, and temperature. In another embodiment, the V-to-I circuit includes compensation circuitry for process and temperature only. There is no need for supply voltage compensation because the supply voltage for the V-to-I converter circuit is provided from a supply that has been linearly regulated and preferably built-in on the chip.

Abstract: A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in the input structure of each amplification stage, and metal lines in the ring and from the ring to the amplification stages over an n-well improve noise immunity and tolerance. The first current mirroring stage utilizes an input current to generate a first voltage controlling a series of differential delay cells connected in a ring topology that forms the ring oscillator. The second mirroring stage utilizes a precision current to generate a second voltage controlling at least one amplification stage, which converts corresponding delay cell output signals to a single-ended logic level signal compatible with external circuitry needs.