Abstract: A hardware accelerator computes a scalar dot product given by ?i=0N?1diPi where di is a scalar of length b bits and Pi is an element in a group. The hardware accelerator includes a plurality A of accumulators addressed by corresponding contiguous partitions of the scalar di, each partition being of length c such that A = ? b c ? and each accumulator containing a plurality B of buckets where B=2c. The value of Pi is entered into each empty accumulator bucket whose value corresponds to the weight of the respective partition associated with the corresponding accumulator or is added to a non-zero value that is already in the bucket, the sum replacing the previous value. An accumulator sums the values in the respective buckets of each accumulator so as to derive A sums, and sums the A computed sums to derive the scalar dot product.

Abstract: A command processing system facilitates pipeline configuration. Each stage of a packet processing pipeline may access certain memory locations for processing of a data packet as it passes through each stage. The command processing system facilitates changing the memory locations in an atomic manner.

Abstract: A command processing system facilitates pipeline configuration. Each stage of a packet processing pipeline may access certain memory locations for processing of a data packet as it passes through each stage. The command processing system facilitates changing the memory locations in an atomic manner.

Abstract: Disclosed are various embodiments of configurable allocation of hardware resources. In one embodiment, a processing device includes a configurable communication grid including a plurality of crossbars interconnected by intercommunication paths in a geometric configuration and a plurality of pipeline elements distributed within the configurable communication grid. Each crossbar is designed to direct communications received at an input to a selected output. Each pipeline element is communicatively coupled to an output of a first crossbar adjacent to the pipeline element and an input of a second crossbar adjacent to the pipeline element. In another embodiment, a process matrix includes a plurality of pipeline elements interconnected by a configurable communication grid. The configurable communication grid includes intercommunication paths connecting crossbars in a geometric configuration.