Patents by Inventor Michael Asbury Woodmansee

Michael Asbury Woodmansee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SECURE EXECUTION FOR MULTIPLE PROCESSOR DEVICES USING TRUSTED EXECUTING ENVIRONMENTS
    Publication number: 20230103518
    Abstract: Apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. In at least one embodiment, a parallel processing unit (PPU), such as a graphics processing unit (GPU), operates in a secure execution mode including a protect memory region. Furthermore, in an embodiment, a cryptographic key is utilzed to protect data during transmission between the accelerators.
    Type: Application
    Filed: September 24, 2021
    Publication date: April 6, 2023
    Inventors: Philip John Rogers, Mark Overby, Michael Asbury Woodmansee, Vyas Venkataraman, Naveen Cherukuri, Gobikrishna Dhanuskodi, Dwayne Frank Swoboda, Lucien Burton Dunning, Mark Hairgrove, Sudeshna Guha
  • IMPLEMENTING TRUSTED EXECUTING ENVIRONMENTS ACROSS MULTIPLE PROCESSOR DEVICES
    Publication number: 20230094125
    Abstract: Apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. In at least one embodiment, a parallel processing unit (PPU), such as a graphics processing unit (GPU), operates in a secure execution mode including a protect memory region. Furthermore, in an embodiment, a cryptographic key is utilized to protect data during transmission between the accelerators.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Philip John Rogers, Mark Overby, Michael Asbury Woodmansee, Vyas Venkataraman, Naveen Cherukuri, Gobikrishna Dhanuskodi, Dwayne Frank Swoboda, Lucien Burton Dunning, Mark Hairgrove, Sudeshna Guha
  • Memory interface design having controllable internal and external interfaces for bypassing defective memory
    Patent number: 9946658
    Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: April 17, 2018
    Assignee: NVIDIA Corporation
    Inventors: Michael Asbury Woodmansee, J. Arjun Prabhu
  • MEMORY INTERFACE DESIGN
    Publication number: 20150149713
    Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Nvidia Corporation
    Inventors: Michael Asbury Woodmansee, J. Arjun Prabhu